FPGAs and Programmable Solutions
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
178 Discussions

Intel® announces Agilex™ 7 FPGAs Enhanced for Datacenter and Network Infrastructure Workloads

0 0 2,416

Intel also demonstrates new Accelerated Virtual Cell Site Router Solution and mMIMO Whitebox development platform based on Intel Agilex 7 FPGAs at MWC

Intel's new Intel Agilex® 7 FPGAs and SoCs (AGI 041) announced at Mobile World Congress (MWC) in Barcelona are designed to enable the creation of high-speed, low-latency, secure infrastructure in modern data center, communications, and enterprise networks. These devices can be used as the foundation for developing advanced SmartNICs and Infrastructure Processing Units (IPUs) that manage high-speed storage and acceleration servers with connections to multiple server CPUs over several independent PCIe 5.0 ports while supporting 100G, 200G, and 400G Ethernet data center infrastructure connectivity. Intel AGI 041 FPGAs and SoCs feature a new core die containing 4 million logic elements (LEs), 335 Mbits of M20K, and dual embedded SRAMs (eSRAMs) in the programmable-logic fabric, along with four hardened, high-performance, 200G crypto blocks that can be combined to support 400G and 800G cryptographic tasks. These new devices are targeted at meeting current and future needs of data center infrastructure, Cloud Service Providers (CSPs), and 5G Communications Service Providers (CoSPs).


The Intel Agilex® 7 FPGAs and SoCs (AGI 041) are the latest members in the Intel Agilex 7 FPGA I-Series product family.

These new I-Series devices also incorporate F-tiles with 116 Gbps SERDES transceivers and R-tiles each with PCIe 5.0 controllers and transceivers. The R-tiles incorporated in the AGI 041 FPGAs and SoCs, support a multi host deployment. Each upgraded R-tile in these new devices support Compute Express Link (CXL) 2.0 and can connect to multiple independent CPU hosts over independent PCIe connections. These independent PCIe 5.0 and CXL 2.0 ports greatly extend host connectivity and will prove especially useful in data-center applications where one FPGA or SoC can be used as an accelerator for as many as six Intel® Xeon® CPUs, communicating over six independent PCIe 5.0 x8 connections.



R-tiles in the Intel Agilex 7 FPGA and SoC FPGA (AGI 041) support multi-host connectivity through truly independent PCIe 5.0 and CXL 2.0 ports

You can expect to see Intel customers and partners leverage the benefits of these new devices in IPU applications requiring 400GbE bandwidth. According to Sandra Rivera, Executive Vice President and General Manager of the Data Center and AI Group at Intel Corporation, IPUs and other data center applications currently constitute the fastest growing market for Intel programmable logic devices.
Intel also exhibited two FPGA-related demonstrations at MWC: a massive MIMO (mMIMO) Whitebox hardware development platform and an Accelerated Virtual Cell Site Router Solution:

Intel® eASIC™ N5X080 Devices Supporting 400G

Intel® eASIC™ devices are structured ASICs, an intermediate technology between FPGAs and standard-cell ASICs. eASIC devices provide lower unit cost and lower power consumption compared to FPGAs, while providing faster time to market (TTM) and lower non-recurring engineering (NRE) costs compared to standard-cell ASICs. Designed for SmartNIC and IPU applications Intel eASIC N5X080 devices include 8.77M eCells and 229Mbits of M10K memory blocks coupled with 1 MB of Mega SRAM memory. Two 200G Ethernet MACs are included with 8x 53G transceivers to support up to 400G Ethernet connectivity. For multi-host connectivity PCIe 5.0 controllers are included supporting x8 or 2 x4 configurations each. These features parallel those of Agilex 7 AGI 041 FPGAs and provide a logical step towards volume deployment once the FPGA implementation is proven and can be hardened into a lower cost and power Intel eASIC N5X080 device.


Intel eASIC N5X080 Structured ASIC Device Supporting 400G Networking, PCIe 5.0 multi-host connectivity, and additional 8MB on-chip memory.

MIMO Whitebox on an Intel Agilex 7 FPGA AGF027/014 R24C dual F-tile package:

The new Intel mMIMO Whitebox serves as a hardware-development platform for Intel's mMIMO enablement package. The mMIMO Whitebox is powered by Intel Agilex 7 FPGAs, each equipped with two F-Tiles, and includes all the essential fronthaul interfaces, data converters with integrated digital front ends (DFEs), and an integrated RF front end (RFFE). The mMIMO Whitebox is part of a comprehensive platform for developing mMIMO radio applications.

The mMIMO Whitebox supports the Control Plane (C-Plane), User Plane (U-Plane), and Synchronization Plane (S-Plane), includes IEEE1588 and SyncE, and features a precision timing protocol (PTP) software stack and servo to meet O-RAN enhanced O-RU specifications including full and partial timing support for telecom profiles.

As an open platform, the mMIMO Whitebox can be combined with Intel's extensive Open RAN IP library - which includes mMIMO beam forming IP – or other third-party IP to create a complete mMIMO Open RAN radio product. The versatile mMIMO Whitebox can be used for proof of concept, lab validation, indoor field testing, limited field trials, or as the foundation for production hardware.


Intel’s Accelerated Virtual Cell Site Router Solution on an Intel FPGA-Based SmartNIC N6000-PL Platform using Intel Agilex 7 FPGAs

CoSPs are constantly looking for additional scalability and operational efficiencies. Virtualizing Radio Access Networks (RANs) is one way to bring these desirable capabilities to 5G deployments. One method used to create a virtualized RAN (vRAN) is to virtualize the cell-site router (CSR), which helps CoSPs boost their ability to monetize their services. The virtualized CSR (vCSR) aggregates mobile data traffic from one or more radio towers at a cell site prior to transporting the traffic back to a CoSP’s core network. Intel’s vCSR solution also supports network slicing, which allows operators to further monetize individual services.
This end-to-end wireless communication demonstration at MWC showcased the benefits of Intel’s Accelerated Virtual Cell Site Router Solution using an Intel Agilex 7 FPGA-based SmartNIC N6000-PL Platform. The Intel Accelerated vCSR solution features an integrated vRouter function (the vCSR) with O-RAN-compliant precision timing coupled with optional integration of a fronthaul gateway (FHGW) and optional baseband acceleration. Several vendors including SuperMicro, Kontron, and WNC support the Intel Accelerated vCSR solution.
The demo’s vCSR integrated vRouter function handles L2 traffic management and L3 routing. A Primary Reference Timing Clock (PRTC) generated by the N6000 SmartNIC provides ORAN-compliant lower layer split, LLS-C3 timing synchronization. This solution supports the Juniper Networks Cloud-Native Router, which provides commercial-grade, high-performance, scalable routing, delivering a state-of-the-art solution for the routing plane integrated with an MPLS data-plane developed by Intel.
This demonstration highlights how an FPGA-accelerated vCSR solution can significantly reduce datapath latency and free up host server processor cores for revenue-generating functions by porting the network routing and control stacks to the Intel Agilex 7 FPGA’s hard processor subsystem (HPS) cores. The MWC demo showed that a vCSR can provide the timing accuracy required for 5G Class B and C systems while supporting interoperability. Because it’s based on standard, open application programming interfaces (APIs) and non-proprietary software, this vCSR solution removes vendor lock-in, gives CoSPs and other customers more choices, and simplifies network deployment and troubleshooting.

Click the links below for more information about the new announcements at MWC: