Intel has shipped more than 10 million chiplets in our FPGA products and has a long history of leveraging chiplet-based manufacturing to deliver the latest innovations in programmable logic devices to our customers. Intel pioneered this significant trend in FPGA development when we explored the use of chiplets connected to a core FPGA die way back in. Using Intel EMIB (Embedded Multi-Die Interconnect Bridge) packaging technology, we used chiplets to add advanced I/O functions and closely coupled DRAM in the form of HBM (high-bandwidth memory), starting with our first Intel® Stratix® 10 FPGA in 2016. We continue to use chiplets and EMIB technology in Intel Stratix FPGAs and our most advanced FPGAs: the Intel Agilex® FPGA families.
Chiplets provide three major benefits to the design and manufacture of Intel programmable logic devices:
- Faster time to market for next-generation technologies
- Flexibility to mix and match the optimal IP, foundry, and process technologies for any desired set of product capabilities
- Building higher capacity semiconductors than is possible with monolithic technology
Chiplet-based device manufacturing using EMIB packaging technology has become a major enabling technology that has allowed Intel to innovate in the FPGA arena rapidly. First, it has allowed the company to develop a broad family of Intel Stratix 10 FPGAs are composed of many variants that focus on capabilities that customers value, including integrated processors, high-data-rate transceivers, high-memory bandwidth, and high-bandwidth processor interfaces. Recently, Intel has used EMIB technology to infuse the same design flexibility into our newer Intel Agilex 7 and Agilex 9 FPGA product families. The company’s chiplet and EMIB technologies are the main enablers for this product leadership. Chiplets are the foundation of a long line of product “firsts” for Intel FPGAs and SoCs:
- February 2018: First FPGA with 58Gbps PAM4
- August 2019: First FPGA support PCIe 4.0
- June 2020: Demonstration of 2Tbps chip-to-chip optical interconnect
- April 2022: First FPGA to be certified by PCI-SIG for PCIe 5.0 x16 operation at 32GT/s
- September 2022: FPGA with the highest bandwidth in-package ADCs and DACs for Direct RF conversion
- March 2023: First FPGA in production with 116Gbps PAM4 transceivers
- May 2023: First FPGA with PCIe 5.0 and CXL hardware support
The most recent example of chiplets in Intel Agilex FPGAs is the announcement last May that Intel is now shipping Intel Agilex 7 FPGAs and SoCs that incorporate R-tiles, which add PCIe 5.0 and CXL (Compute Express Link) capabilities to the devices as shown in Figure 1 below. Intel is the first FPGA vendor to ship devices with PCIe 5.0 transceivers listed by the PCI-SIG for compliance at the full 5.0 x16 rate, and the CXL interfacing capability incorporated into R-Tile devices are the industry’s first such transceivers to be implemented with hard IP on chip.
Figure 1: Intel is the first FPGA vendor to ship devices with PCIe 5.0 and CXL interfacing capability, and the company’s chiplet and EMIB technologies are the main enablers for this sort of product leadership.
Using these devices, Intel customers can seamlessly connect their FPGAs with high-end CPUs, such as 4th Gen Intel® Xeon® Scalable processors, using the fastest available interfaces to accelerate targeted data center and high-performance computing (HPC) workloads. (See “Intel Launches Agilex 7 FPGAs with R-Tile, First FPGA with PCIe 5.0 and CXL Capabilities.”)
Intel Agilex 7 FPGAs and SoCs now incorporate four different interface chiplets, called tiles:
- E-Tiles, with 58Gbps PAM4 and 28.9Gbps NRZ transceivers
- P-tiles, with PCIe 4.0 and 16Gbps transceivers
- F-Tiles, with PCIe 4.0, 116Gbps PAM4, 58Gbps PAM4, and 32Gbps transceivers
- R-Tiles, with PCIe 5.0, CXL, and 32Gbps transceivers
All these chiplets connect with the Intel Agilex 7 devices’ core FPGA fabric chiplet through EMIB interfaces and can be incorporated into the FPGA’s or SoC’s package using a mix-and-match approach. In addition, the Intel Agilex 7 FPGAs and SoCs M-Series offer integrated, in-package HBM2E DRAM memory, also connected via EMIB technology, for applications that require large amounts of high-speed memory to be located as close to the FPGA die as possible. The HBM2E memory stacks add 16 or 32 Gbytes of DRAM to the M-Series devices.
Chiplet-based FPGA development is not restricted to the digital domain. Intel recently created a portfolio of analog-enabled Intel FPGA Direct-RF Series FPGAs that can perform direct RF signal conversion for multiple analog input and output channels at groundbreaking rates as fast as 64 gigasamples/sec (Gsps) over as many as eight channels. The programmable logic devices in this new Direct-RF Series FPGA portfolio employ EMIB and chiplet interconnect technology to combine RF-capable ADC and DAC chiplets with Intel Stratix 10 FPGA and Intel Agilex FPGA fabric die. These new Direct-RF Series FPGAs enable design solutions for many RF applications and can provide solutions to RF design challenges that were unsolvable with any previously existing electronic technology. (For more information on the Intel analog-enabled FPGA portfolio, see the “Intel Agilex® 9 FPGA Direct RF-Series Whitepaper.”)
Currently, there are more than twenty chiplets developed as part of the ecosystem stemming from Intel’s custom logic products. These chiplets encompass a broad range of functionality, built on several different process nodes from multiple foundries and sourced from different developers. Functions in the library already include FPGA fabric die from the Intel Stratix 10 and Intel Agilex FPGA families, high-speed transceivers, optical I/O, analog data converters, application-specific computing, and five chiplets from Defense Industrial Base suppliers, as shown in Figure 2 below. The chiplets from this library are available for integration with Intel Structured ASICs and full-custom ASICs as well.
Figure 2: A broader open chiplet ecosystem based on UCIe will accelerate product development throughout the industry and allow Intel to add many more functions to our FPGAs, Structured ASICs, and full-custom ASICs.
Looking forward, Intel fully intends to extend our leadership in chiplet technology. Last March, Intel, along with Advanced Semiconductor Engineering Inc. (ASE), AMD, Arm, Google Cloud, Meta, Microsoft Corp., Qualcomm Inc., Samsung, and TSMC (Taiwan Semiconductor Manufacturing Co.), announced the establishment of an industry consortium to promote an open die-to-die interconnect standard called Universal Chiplet Interconnect Express (UCIe). Intel originally developed the UCIe standard and then donated the UCIe work as an open specification that defines the in-package, chiplet-to-chiplet interconnect. (To learn more about the UCIe consortium, please visit www.UCIexpress.org.)
“Integrating multiple chiplets in a package to deliver product innovation across market segments is the future of the semiconductor industry and a pillar of Intel’s IDM 2.0 strategy,” said Sandra Rivera, executive vice president and general manager of the Datacenter and Artificial Intelligence Group at Intel. “Critical to this future is an open chiplet ecosystem with key industry partners working together under the UCIe Consortium toward a common goal of transforming the way the industry delivers new products and continues to deliver on the promise of Moore’s Law.”
The UCIe consortium’s standards should enable a broader open chiplet ecosystem that will accelerate product development throughout the industry. This sort of chiplet-based, mix-and-match approach to FPGA development, as suggested in the right-hand box in Figure 2 above, is very much in line with Intel’s recently announced IDM 2.0 strategy, as stated by Sandra Rivera in the above quote. Looking forward, Intel plans to extend our leadership in chiplet technology with the use of UCIe in future Intel FPGAs, and the company plans to keep our FPGAs and SoCs at the forefront of the programmable-logic market using this technology, as we have now for nearly a decade.
Learn more about chiplet architecture in Intel FPGAs here.