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Intel shares update on Heterogeneous Integration and SHIP program at 55th iMAPS Packaging Conference

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At the 55th International Symposium on Microelectronics Symposium (iMAPS) held in Boston, Intel’s John Sotir, Senior Director of Military, Aerospace & Government Business Unit and State-of-the-Art Heterogeneous Integration Packaging (SHIP) within Intel’s Programmable Solutions Group, presented a comprehensive look at the company’s focus on using multi-chip packages (MCPs), and Intel’s advanced domestic packaging capabilities to implement heterogeneous integration (HI), and MCPs to drive a giant leap in SWAP (size, weight and power) improvements for the US Government and the Defense Industrial Base (DIB). The company currently has multiple engagements with the US Government in multiple development programs–including the S2MARTS/NSTXL SHIP program–which is allowing Intel to drive the design and prototyping of diverse MCP configurations, , within military and aerospace applications in particular.

Part of this program, and part of Intel’s extended corporate strategy, involves significant investments in onshore manufacturing and advanced packaging technologies. Intel is addressing the revitalization of US semiconductor manufacturing on multiple fronts. One indicator of Intel’s key role in this revitalization effort is the company’s active role in the recent passage of the CHIPs act. Intel’s CEO Pat Gelsinger was perhaps the most visible part of Intel’s participation in this groundbreaking legislation, but it was truly a company wide effort.

Sotir’s presentation focused on the methodology that Intel has developed in tight collaboration with the US Government and the DIB to accelerate the package, assembly, and test from design start to prototyping by leveraging the company’s state-of-the-art (SOTA) integration and advanced packaging technologies for semiconductor MCPs. The ecosystem heavily leverages the improvements to SWAP and the dramatic increase in performance per watt enabled by this program.

Intel has three major goals for this program:

  • Establish multi-chip package processes leveraging commercial capability to support the US Government and its DIB
  • Advance existing figures-of-merit through heterogenous MCPs versus discrete performance and power
  • Accelerate interface standards, protocols, and security for heterogeneous MCPs

The fruits of the SHIP program are already starting to appear. For example, Intel announced a new analog-enabled FPGA and SoC portfolio in September at the Intel Innovation event held in San Jose, California. This portfolio delivers world-leading performance for programmable logic devices with integrated analog-to-digital and digital-to-analog converters (ADCs and DACs) with sample rates as high as 64 Gsamples/second. These devices can be used for Direct RF applications in myriad defense and communications applications. Nothing currently on the market comes close to this RF performance and these new programmable devices enable completely new applications, formerly unachievable with available technology.

Perhaps an even more important program objective, however, is Intel’s focus on developing a library of semiconductor chiplets with selected partners that serve to enable rapid development of new MCP devices to meet specific and specialized needs in both the military/aerospace and commercial markets. Intel’s approach and its emphasis on reusability has been fully embraced by the SHIP program with its modular approach to developing new devices by DIB contractors in partnership with Intel.

To learn more about the analog-enabled FPGA and SoC portfolio, or to further explore Intel’s MCP design and manufacturing capabilities, contact your local Intel Sales representative.