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Intel to Present Seven Papers and Two Demos at GOMACTech, March 20-23

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Intel will have a large and visible footprint at the upcoming GOMACTech conference being held in San Diego on March 20-23. GOMACTech was established in 1968 as the premier conference for discussing new developments in microcircuit applications for government systems and focuses on advances in systems being developed by trusted suppliers for the US Department of Defense and other US government agencies. This year’s conference theme is “Microelectronics – the Engine to Keep the US Moving Forward,” which reflects the large amount of US government activity in the semiconductor sector, including the recent passing of the CHIPS and Science Act. At this year’s GOMACTech, Intel will be presenting or co-presenting seven papers and will have two demonstrations at specific times in Booth 203 on the exhibit floor, shared with  National Security Technology Accelerator (NSTXL).

Of the seven papers related to Intel® FPGAs being presented at GOMACTech, three are by Intel authors. Two of these three papers discuss the new Intel® Direct RF FPGAs, which employ Intel’s embedded multi-die interconnect bridge (EMIB) and Advanced Interconnect Bus (AIB) tile interconnect technology to combine RF-capable analog-to-digital converters (ADCs) and digital-to-analog-converters (DACs) with the Intel Stratix® 10 FPGA and Intel Agilex FPGA die. EMIB and AIB packaging technologies currently provide low latency and power consumption when converting between the analog and digital domains.

The two papers are:

  • “Direct RF FPGAs with Integrated 64 GSPS Data Converters,” which discusses the replacement of conventional RF/IF-conversion circuits with direct RF conversion to improve size, weight, and power (SwaP) in radar, EW, and communications systems; and
  • “Performance Metrics for Direct RF Transceivers: An Update to Traditional Metrics and Implementation Example” discusses appropriate methods for evaluating direct RF designs and producing meaningful comparisons with conventional RF/IF-conversion architectures.

The last Intel paper, “A Comparative Study on DFTs in FPGA,” discusses different approaches to an efficient methodology for implementing discrete Fourier transforms (DFTs) using FPGAs. This paper also discusses design tradeoffs taking transform size into account. Of course, DFTs are extremely useful for developing direct RF systems, so this paper also relates to Intel’s Direct RF-Series FPGAs.

The other four papers involve redacting or obfuscating pieces of a hardware design to protect sensitive or confidential design intellectual property (IP) when a chip implementing that design is manufactured by an untrusted or offshore vendor. The redaction process removes a portion of an SoC’s design and moves it to a bitstream-based programmable fabric. The manufactured SoC is not operational until it is paired with a bitstream built from the redacted part of the design and the secure bitstream is only available to trusted providers. The redaction is performed by a tool called RIPPER, which has been developed by researchers at the University of Florida and Intel.

The first of these papers, titled “Low Overhead Hardware Redaction Using Bitstream Compaction,” lists authors from the University of Florida and Intel. This paper provides a detailed description of the RIPPER redaction tool and its use. The second paper, titled “ATPG and Test Methods for Redacted IP,” discusses the effects of design redaction on automatic test pattern generation (ATPG). The authors of this paper are also from the University of Florida and Intel. “Red Teaming Methodology for Design Obfuscation,” co-authored by people at the Institute for Systems Research, located at the University of Maryland, and Intel proposes a red-team method for evaluating the security of an obfuscated design. Lastly, the paper titled “Formal Equivalence Checking for Locked and Redacted Hardware” were authored by people at the University of Florida and Intel. This paper proposes a sequential equivalence checking technique that can be used for formal analysis of obfuscated designs.

During specific times, two Intel demos are in Booth 203:

  • A brief overview of the new Direct RF-Series FPGAs and the Intel Direct RF FPGA Evaluation Platform, a tool for evaluating the dynamic performance of the Direct RF-Series FPGAs; and
  • A demonstration of the RIPPER design redaction tool, which is used to protect a design’s critical or confidential IP during SoC and system manufacturing, as discussed in several of the papers listed above.

For more information about Intel Direct RF-Series FPGAs, click here, or read “Intel Delivers a Game-Changing, Analog-Enabled Direct RF FPGA Portfolio.”