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Introducing Intel’s Next-Generation of Nios® Soft-Core Processor: Nios® V Processor

Daniel_Michek
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Nios has long been the most popular soft-core processor for use in field-programmable gate array (FPGA) designs. Soft-core processors can be customized and instantiated on an FPGA, using the programmable logic fabric of an FPGA to add easily-programmable microcontroller or processor cores to a logic design. Nios processors have been used in FPGA designs for everything from simple state machine control to booting operating systems such as Linux and running application code.

Developers have enjoyed the flexibility and customizability of the Nios processor, as it gives them the ability to efficiently add any number of software-programmable cores to a digital design, amplifying the flexibility of FPGAs. Over the years, the Nios processor has accumulated a large ecosystem of developers, tools, software, and software intellectual property (IP).

Now, Intel has launched the next generation of soft processors for Intel® FPGAs—The Nios® V Processor. The Nios V processor is based on the open-source RISC-V Instruction Set Architecture (ISA). Leveraging RISC-V in promises to dramatically expand the already large Nios processor ecosystem, and deliver even greater flexibility and performance to developers of FPGA-based systems.

The initial Nios V processor, dubbed Nios V/m is a microcontroller (MCU). It is based on the RV32IA section of the RISC-V specification with atomic extensions, a 5-stage pipeline, and AXI4 interfaces, making Nios-V/m a very capable MCU. It also includes support for the bare-metal Intel Hardware Abstraction Layer (HAL), and uC/OS-II real-time operating system. These features should enable seamless ports of existing Nios II processor designs to Nios V processor designs.

The Nios V processor raises the performance bar significantly, with more than 5X the performance of Nios II/e processor. The Nios V processor achieves 0.462 DMIPS/MHz versus the Nios II processor’s 0.107 DMIPS/MHz, and achieves an Fmax of 566 MHz on Intel® Agilex™ FPGAs, versus 400 MHz for Nios II processor. The Nios V processor is also fully compatible with other Intel FPGA families, including Inte Cyclone® 10 GX FPGA Intel® Arria® 10 FPGA, and Intel® Stratix® 10 FPGA.

The Nios processor takes advantage of the M20K embedded memory blocks available in Intel FPGAs, bringing efficient access to the general purpose register file. The Nios V/m processor duplicates register files so that two different operands for an instruction are available in a single cycle and write the same values to the memories.

The Nios V/m processor also includes a debug module, providing on-chip emulation features that allow you to control the processor remotely from a host PC. PC-based software debugging tools communicate with the debug module providing the ability to download programs, start and stop execution, set breakpoints and watchpoints, and analyze the contents of registers and memory.

Intel plans to add additional Nios V processor variants including a “General-Purpose” version, an “Application Class” version, and a “Linux-Capable” version, which will be a 64-bit processor capable of running a Linux kernel.

Intel plans to add additional Nios V variants including an “Application Class” version and a “Linux-Capable” version, which will be a general purpose processor capable of running a Linux kernel. 

Nios V processors use the same simple design flow as Nios II processors and are available in the Intel® Quartus® Prime Pro Edition Software starting with version 21.3. Licensing which is available at no cost through Intel’s Self Service Licensing Center.

Learn more at the Nios V processor session on-demand at Intel FPGA Technology Day (IFTD) 2021.