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SAP accelerates compression workload in POC with Intel® OFS

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A recent development project by developers demonstrates how easy it is to accelerate containerized workloads using an Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) and The project moved an FPGA-accelerated compression algorithm called Re-Pair into a container and made it available as a service to customers using SAP HANA, a relational database management system. This project serves as a proof of concept (PoC) and demonstrates that FPGA-accelerated application workloads like Re-Pair can easily migrate into the pervasive containerized environments used in modern data centers without significant porting effort or major challenges.

The SAP HANA relational database encodes columnar data using dictionaries to permit fast access to stored data. These string dictionaries become quite large and are usually compressed to reduce their footprint in memory. Although conventional compression algorithms such as LZ77, LZR, LZSS, LZMA, and ZStandard are routinely used to compress large blocks of data, these algorithms do not compress string dictionaries efficiently because the entire dictionary must be decompressed before accessing a dictionary entry. A compression algorithm called Re-Pair is better suited to this task. However, Re-Pair is not widely used because it’s computationally intensive. The massively parallel processing capabilities of an FPGA can be applied to the Re-Pair algorithm to accelerate the algorithm’s execution speed while consuming relatively little operating power.

SAP developers had already implemented the Re-Pair algorithm in stand-alone form using the Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs, OpenCL, and the Intel® FPGA PAC D5005. They elected to migrate this accelerated workload to a containerized environment as a PoC project to demonstrate how computationally intensive workloads like Re-Pair can benefit from FPGA-based acceleration and to determine the amount of effort needed to migrate the workload.

SAP’s developers took the existing Re-Pair implementation written with OpenCL and ported it using Intel OFS, which eases the development and deployment of workloads using Intel or third-party platforms powered by Intel FPGAs. Recompiling the Re-Pair compression algorithm workload using Intel OFS required minimal code changes, primarily around the   new Unified Shared Memory (USM) Board Support Package (BSP). Intel OFS provides standard interfaces and application programming interfaces (APIs) that accelerate workload development and enable code reuse when accelerating workloads with FPGAs.

The original Re-Pair code did not need modification. It only needed to be recompiled with Intel OFS libraries. The recompiled code was used to build a host executable, which ran on a Garden Linux kernel installed on a server with an Intel FPGA PAC D5005 card plugged into one of its PCIe slots.

Garden Linux is a highly customizable Debian GNU/Linux derivative that builds small, auditable Linux images, which are well suited to distributed and containerized computing systems. SAP uses Garden Linux for its cloud platform as do many other cloud providers. Intel OFS Device Feature List (DFL) FPGA drivers have been included in the Garden Linux kernel since release 5.15. SAP’s developers also took advantage of the high-level design (HLD) shim included with Intel OFS to allow the FPGA-accelerated Re-Pair workload to communicate with application code running on the server’s CPU through automatically constructed protocols. SAP developers created their Re-Pair workload PoC and deployed it using Docker containers.

Because the SAP Re-Pair PoC project employed Intel OFS, which supports both OpenCL and the oneAPI programming model, SAP developers are already planning a project to migrate the Re-Pair code from OpenCL to the oneAPI programming model and then moving from the Intel FPGA PAC D5005 card, which is based on an Intel® Stratix® 10 FPGA, to a faster, more powerful accelerator card based on an Intel® Agilex™ FPGA. This migration path will help SAP to achieve more performance and better power efficiency from the FPGA-accelerated Re-Pair Algorithm. As it did with the Intel FPGA PAC D5005, Intel OFS will ease the migration to the new FPGA accelerator card based on the Intel Agilex FPGA.

For more details about this SAP PoC project, please download the White Paper titled “Intel® FPGA Programmable Acceleration Card D5005.” You can also learn more about SAP’s development of the accelerated Re-Pair workload by reading “SAP Prototypes String Compression Algorithm.”