Pathfinding the way towards a future where chip-to-chip interfaces exceed the bandwidth and power limitations of electrical connections, Intel, in collaboration with Ayar Labs, have achieved new heights by demonstrating 4-Tbps communication between semiconductor devices integrating advanced FPGA and optical chiplets.
As a performer for the DARPA PIPES (Photonics in the Package for Extreme Scalability), Intel’s Programmable Solutions Group (PSG) created a demo highlighting 4-Tbps chip-to-chip communication with Intel® FPGA co-packaged optics MCP (Multi-Chip Package). This demo was first presented at the DARPA ERI (Electronics Resurgence Initiative) summit in Seattle last August, and then at Hot Chips conference and OCP (Open Compute Project) summit soon after.
On November 7, Dr. Carl McCants (DARPA), Sergey Shumarayev (Intel), and Allen Chan (Intel) presented this demo at the American Possibilities: A White House Demo Day event in Washington, DC, by invitation from DARPA, as one of the 45 demos to showcase how federal investment unlocks innovations for a better future. The demos were grouped in six aspirational areas, and our demo is categorized as Opportunity, apropos of what the demo opens up – opportunities to create new data center and communication systems with this faster, lower-latency, and lower-power optical data transfer, removing the I/O bandwidth bottleneck. President Joe Biden also visited the demo and spent some time going through each of the demos at the event.
The demo relies on Intel’s FPGA chiplet leadership strategy of rapidly integrating industry-first capabilities into Intel FPGAs via co-packaged chiplets. We started this with the DARPA CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program, where the team created an MCP with Intel® Stratix® FPGA die and data converter chiplets that laid the foundation for the Intel® FPGA Direct RF-Series portfolio. On the PIPES program, we built an MCP with Intel® 10-nm FPGA co-packaged with Ayar Labs’ TeraPHY™ Optical I/O chiplets and Intel® F-tile chiplets.
The same demo will also be available for viewing at Supercomputing 2023 in Denver, Colorado at Ayar Labs’ booth. Come and see how the MCP integrated on a PCIe CEM form-factor board with the Ayar Labs SuperNova™ laser talking to each other at 4 Tbps with BER of <1e-12.
This important demonstration represents the first steps towards a future where chip-to-chip communication bandwidth can advance by orders of magnitude, unfettered by the limitations of electrical connections. Using optical interfaces to provide higher bandwidth for chip-to-chip communications has the potential to enable even greater advances across all industries and human endeavors that rely on data, including high-performance computing, data centers, communications, AI, medicine, advanced scientific research, and more.
This research was, in part, funded by the U.S. Government. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government.