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Silicom Showcases FPGA SmartNIC Acceleration Cards for O-RAN Apps at MWC Barcelona 2022

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The new Silicom FPGA SmartNIC N6010/N6011 PCIe add-in cards, announced last December, are high-performance OEM hardware acceleration platforms targeting mobile 4G and 5G Baseband Units (BUs) and Distributed Units (DUs). These cards and their associated IP provide an Open Radio Area Network (O-RAN) standards-compliant Layer 1 High PHY solution using open, fully programmable platforms based on an Intel® Agilex™ FPGA and an Intel® Ethernet Controller E810. Silicom is showcasing the Silicom FPGA SmartNIC N6010/N6011at this year’s Mobile World Congress (MWC) Barcelona 2022.

According to Silicom, Silicom FPGA SmartNIC N6010/N6011serve a variety of use cases including:

  • 4G/5G vRAN Acceleration
  • Network Function Virtualization (NFV)
  • Multi-Access Edge Computing (MEC)
  • Video Transcoding
  • Cyber Security
  • High-Performance Computing
  • Finance

5G Open Radio Area Network (O-RAN) systems are the primary target for Silicom FPGA SmartNIC N6010/N6011. A collection of standards managed by the O-RAN Alliance and 3GPP define 5G O-RAN. These standards support disaggregation, open application programming interfaces (APIs), and multi-vendor interoperability, which are all very attractive characteristics for Mobile Network Operators (MNOs) seeking to build flexible, responsive networks. The 5G O-RAN standards are specifically designed for building virtualized RAN (vRAN) systems that run on commercial off-the-shelf (COTS) servers. Because O-RANs enable a greater level of network flexibility and supports multi-vendor deployments, they have been embraced by an extensive ecosystem of companies, who are now busily designing products, systems, software, and solutions for O-RAN environments.

In addition, O-RAN standards disaggregate the baseband unit into a centralized unit (CU) and one or more distributed units (DUs). A DU handles real-time Layer 1 and 2 scheduling functions while the CU is responsible for non-real-time L2 and L3 processing. Because of its real-time nature, the DU’s performance benefits from the Silicom FPGA SmartNIC N6010/N6011’s hardware programmability, enabled by its on-board Intel® Agilex™ FPGA. In addition to the Intel Agilex FPGA, the Silicom FPGA SmartNIC N6011incorporates the Intel®Ethernet Controller E810, which increases the SmartNIC’s Ethernet performance. These SmartNIC designs can serve as a Layer 1 offload engine in today’s O-RAN architecture and work in O-RAN LLS-C1 and C2 fronthaul-transport-synchronization configurations. They can be used to build a Layer 1 offload engine with advanced timing synchronization.

Silicom FPGA SmartNIC N6010/N6011 is Silicom’s implementation of the Intel® FPGA SmartNIC N6000-PL Platform, which was announced last year during Intel Architecture Day. It’s an FPGA-based SmartNIC designed for 100GbE network development and builds upon the success of the Intel® FPGA Programmable Acceleration Card (Intel® FPGA PAC) N3000, which is deployed in data centers operated by some of the world’s top Communications Service Providers (CoSPs).

The new Intel® FPGA SmartNIC N6000-PL Platform is based on the Intel Agilex FPGA and the Intel Ethernet Controller E810 and is designed for Intel-based servers. Intel Agilex FPGAs deliver:

  • ~2X better fabric performance per watt compared to competing 7 nm FPGAs*
  • 15% to 20% faster on average than competing 7 nm FPGAs for 5G O-RU functions

Silicom specifically designed the Silicom FPGA SmartNIC N6011 as a 5G O-RAN platform using open Intel® technologies. It is custom designed to meet the real-time processing needs of 5G DUs and can be configured for a wide range of network deployments, including urban locations that need substantial processing power to serve large groups of 5G users. According to Silicom, the company has designed the Silicom FPGA SmartNIC N6011to be the top choice for MNOs seeking a cost-effective, self-contained server that combines flexibility with simplicity. Intel® Network Builders Winners‘ Circle recognized Silicom last November as a Gold-Tier Partner for its work on accelerating 5G, OpenRAN, and Edge solution development.


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*See configuration information at intel.com/performanceindex




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About the Author
Sabrina is Director of Marketing, FPGA Platforms and has over 20 years of experience serving a wide breadth of markets including data center, communications and industrial with a strong technical background in FPGAs. She has a Bachelor of Science degree in Electrical Engineering from San Jose State University.