The Serial Digital Interface (SDI) for broadcast video equipment has been the established standard for interconnecting professional equipment used in the broadcast industry for decades. The SDI equipment list includes video cameras, recorders, monitors, mixers, and PCs. The original SDI specification introduced by The Society of Motion Picture and Television Engineers (SMPTE) in 1989 delivered digital video at 3 Gbps over inexpensive 75-ohm coaxial cable terminated with inexpensive and rugged BNC connectors. Since its introduction, there have been many upgrades to the original SDI specification. The maximum data rate has climbed from 3 Gbps to 6 Gbps, and then 12 Gbps and beyond to support increased video resolution (HD, 4K, and 8K), faster frame rates, and multiple digital audio channels and audio standards. SDI continues to deliver these greatly expanded capabilities over coax, while optical fiber transmission has now been added to extend SDI’s reach.
FPGAs are well-suited for SDI implementations and Intel has developed the SDI II intellectual property (IP) core for Intel® FPGAs and SoC FPGAs that supports HD-SDI single rate mode, 3G-SDI single rate mode, triple-rate mode, and multirate mode. Triple-rate mode supports SD-SDI, HD-SDI, and 3G-SDI while multirate mode supports all the SDI standards in triple-rate mode and adds 6G-SDI and 12G-SDI. Most Intel FPGAs and SoC FPGAs including devices in the Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, Intel® Cyclone® 10, Stratix® V, Cyclone® V, and Arria® V device families support multiple SDI variants and data rates when used with the SDI II IP core.
Intel has just published a video with an SDI demo implemented with an Intel Agilex I-Series FPGA and the SDI II IP core. The demo is based on an SDI retransmit design that does not require an external VCXO for genlocking purposes. Instead, it uses the Intel Agilex I-Series FPGA’s internal transmit phase-locked loop (PLL) on the FPGA’s F-tile in fractional mode. Each Intel Agilex FPGA F-tile has sixteen transmit channels and each of these channels has an independent transmit PLL, which can be clocked with the same reference clock frequency of 140 MHz. This means that the FPGA can support as many as sixteen independent channels running the retransmit design in a single tile. Intel Stratix 10 and Intel Arria 10 FPGAs also have this capability, but do not incorporate as many transmit PLLs and therefore can support only half as many independent channels as the Intel Agilex FPGA.
The demo design uses an Intel Agilex I-Series Transceiver-SoC Development Kit and a 12G-SDI FMC daughter card. Coaxial BNC cables connect the test setup to a test oscilloscope, which is sending and receiving video from the FPGA. The demo uses a color bar standard from a video test generator, transmitted at the 12G-SDI data rate. The resulting alignment jitter through the retransmit design is 0.16 UI, which exceeds the SMPTE mandated specification of 0.3 UI.
Switching the demo to 6G-SDI yields an alignment jitter of just 0.05 UI, while at 3G-SDI the alignment jitter is 0.08 UI. For HD-SDI, the alignment jitter is 0.03 UI. For SD-SDI, the alignment jitter is 0.04 UI. These alignment jitter results demonstrate the low-jitter characteristics of the FPGA’s internal transmit PLL. The demo’s multirate SDI design can retransmit incoming digital video while switching output data rates from SD-SDI to 12G-SDI, all within the alignment jitter compliance range of SMPTE standards.
If you are developing broadcast video equipment that uses any version of the SMPTE SDI standard, you should watch the new video demo based on the Intel Agilex FPGA. Click here.
Multirate retransmission is only one of the many SDI applications that you can develop using Intel FPGAs and the SDI II IP core. For more information about the SDI II IP for Intel FPGAs, including application guidance and design examples, see:
- SDI II Intel FPGA IP User Guide
- SDI Audio Intel FPGA IP User Guide
- SDI II Intel® Arria® 10 FPGA IP Design Example User Guide
- SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
- SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
You must be a registered user to add a comment. If you've already registered, sign in. Otherwise, register and sign in.