In the contemporary landscape of cloud computing, the demand for high-performance, scalable networking solutions continues to surge. SONiC-DASH (Disaggregated API for SONiC Hosts/DASH) is a pivotal open-source initiative that capitalizes on the advanced capabilities of programmable network hardware, such as the Intel® Infrastructure Processing Unit (Intel® IPU) Adapter E2100, to significantly enhance networking within cloud infrastructures. This project surpasses conventional software-centric approaches, addressing critical applications in high-performance network appliances and smart switches. A key innovation within SONiC-DASH is its stateful connection tracking mechanism, which introduces robust state-aware processing into the packet pipeline, enabling efficient and seamless bidirectional communication between virtual machines regardless of their geographic distribution. The architecture is further distinguished by its sophisticated five-stage access control lists (ACL) system, dynamic routing capabilities, and a suite of advanced features including high availability, private link, and service tunneling.
This blog delves on some of the details of the DASH pipeline's architectural framework and performance as deployed on the Intel® IPU Adapter E2100, a high-performance, programmable 200GbE PCIe networking device that combines networking efficiency and intelligent switch functionality. Intel's implementation of the DASH pipeline, programmed using P4, facilitates routing and forwarding processes, as well as multi-tiered ACL management for both inbound and outbound traffic. Currently, our connection tracking implementation operates in software on the IPU’s ARM cores, supporting up to 32 million bidirectional flows with integrated flow aging capabilities. The DASH pipeline is carefully aligned with the IPU hardware architecture, utilizing P4 tables for an optimized, high-level design. Future development aims to fully integrate connection tracking into the hardware pipeline. The existing solution meets the complete SONiC-DASH "baby-hero" test specification, operating as a hybrid software-hardware system on the IPU’s ARM cores and hardware pipeline blocks.
Baby hero scale testing requires rule configuration with 160K outbound routes, 32 inbound routes, 320K ACL rules and support for 32M bidirectional flows. The following graphs show the current performance numbers for baby hero Scenario with one IPU adapter. The solution can achieve a raw CPS of 8.7M TCP connections without background flows and with zero packet drops and a CPS of 3.2M TCP connections with 30M background (pre-established) flows with a 10 sec ageing timer. The PPS rate achieved is 45M.
Figure 1. TCP CPS without Background Flows
Figure 2. TCP CPS with 30M Background Flows
The DASH pipeline is quite complex in terms of both scale and performance. The implementation is expected to be distributed across hardware blocks and the IPU's ARM Compute Complex. The figures shown above represent our initial results for the baby hero phase. As we transition to the full hero scale implementation we will make necessary adjustments to fully leverage the IPU’s hardware blocks, ensuring optimal scalability and performance.
Stay tuned for further updates on hero scale development, near 0 packet drops with background flows, and better performance numbers as we make progress.
Kristina Moore, Principal Product Manager at Microsoft, shared her thoughts on this initiative: “Intel has partnered with Keysight to achieve the notable performance gains for the Intel® IPU E2100. As members of DASH and SONiC, our team at Microsoft closely collaborates with Intel to share contributions and expertise that benefit the open source community."
Namrata is a Director of Software Engineering at Intel driving execution of multiple offload solutions including the Sonic-Dash implementation on Intel(R) Infrastructure Processing Unit E2100 and AI NIC Drivers for AI NICs. She also drives the engineering team for execution and open-sourcing of multiple projects in the areas of P4 based offloads on Intel IPU including OVS/P4-OVS, TLS, P4-Control Plane (IPDK) and P4 enablement in Linux kernel via P4-TC. Before Intel, Namrata has worked in different domains including 5G networks, SDN, and 4G Mobile stack.