Scott Bair is a key voice at Intel Labs, sharing insights into innovative research for inventing tomorrow’s technology.
Highlights:
- APS March Meeting 2024 will run from March 3rd through 8th in Minneapolis, Minn., with other options to attend virtually or at satellite locations around the world.
- Intel will present 12 talks, including information on advances in both quantum computing hardware and software.
- The Intel Quantum SDK v1.1 (a full quantum computer in simulation) includes more powerful programming tools, an open-source compiler front-end allowing user-defined compiler passes, two additional target qubit simulation backends and new customizable qubit noise models,
- Intel’s quantum hardware teams will introduce specifications for the design of next generation spin qubit arrays, analysis of high-volume quantum dot test data, encoded qubit operations, faster readout, as well as introduce Intel’s Quantum Control Processor.
- Sandia National Labs researchers will also present two co-authored talks on qubit characterization and shuttling using Intel’s Tunnel Falls quantum hardware.
This year’s APS March Meeting conference will run from March 3rd through 8th in Minneapolis, Minn., with other options to attend virtually or at satellite locations around the world. Celebrating the 125th anniversary of APS, the 2024 event will host thousands of talks by members of the scientific community on academic and industrial physics, including hundreds on quantum computing.
Intel is excited to present 12 quantum research papers at the conference. The Intel Quantum SDK v1.1 includes a new functional language extension for quantum (FLEQ) that enables flexible and modular development of complex quantum logic. Intel will also introduce research on a qubit control processor for orchestrating the control electronics using inspiration from classical CPU design. Researchers will also demonstrate the full-stack-in-simulation capabilities of the Intel Quantum SDK for evaluating and vetting quantum error correction (QEC) protocols.
The quantum computing hardware teams will present multiple high-fidelity qubit operation results, define qubit specifications for the next generation of scaled qubit arrays, and multiplexing to enable future scaling. Intel will share improved readout, novel and more efficient qubit characterization, and the statistical analysis needed to develop qubits using high volume industrial manufacturing.
Additionally, in June 2023, Intel released its newest quantum research chip, Tunnel Falls, a 12-qubit silicon chip, and made it available to the quantum research community in an effort to expand the scope of quantum research. Intel is excited to see movement toward this goal through two co-authored papers with Sandia National Lab, which will be presented at the conference.
Conference Papers
A Millikelvin CMOS Demultiplexing Chip for Scalable Qubit Addressing
Presenter: Sushil Subramanian
Large-scale silicon qubit control requires accurate biasing and gate pulsing for several terminals of a multi-qubit device. Continuous pulsing enables sequential quantum operations, while simultaneous pulsing on multiple terminals enables real-time cross-talk compensation. Conventional qubit addressing provides DC bias and gate pulsing using commercial instruments at 300 K, while recent innovation in cryo-CMOS control can move select signal generation to 4 K. In both approaches however, cabling, power and noise constraints becomes a bottleneck for controlling large qubit/SET arrays. To address the cabling bottleneck, certain aspects of the control system should be moved closer to the qubits at the mK stage.
This work presents a mK cryo-CMOS demultiplexer chip that uses a single DC bias generator and a single pulse generator as inputs, to demultiplex voltages for up to 64 qubit device terminals and provide both DC bias, and simultaneous and continuous high-speed gate pulses. To further alleviate cabling bottlenecks, a 4 K cryo-CMOS controller provides the control signals and gate pulsing voltage to the mK demultiplexer. Integrated with a foundry manufactured qubit chip on the same PCB, mK cryogenic measurements show multi-terminal characterization of a qubit device.
Comprehensive Quantum Computing Simulation with Intel Quantum SDK v1.1
Presenter: Shavindra P Premaratne
The Intel Quantum SDK is a C++ based toolchain for compiling and executing workloads for seamless classical/quantum program execution. This system is naturally suited for execution of hybrid algorithms due to the tight integration allowed between the classical and quantum code. Simulations using qubit simulators has been a valuable resource for assessing feasibility, establishing limits, and studying scaling aspects of quantum algorithms. The Intel Quantum SDK with v1.1 will allow convenient targeting of four different kinds of qubit simulators each with their own strengths, combined with the powerful optimization capabilities of the compiler toolchain. This talk covers the capabilities and limitations of each of the simulator backends and provides recommended use cases based on examples. It will also explore the asynchronous mode of simulators which allows parallel execution of simulations.
Defining Specifications for Si/SiGe Qubit Devices Using Multiphysics Modeling Methods
Presenter: Fahd Mohiyaddin
The design of large-scale spin qubit arrays and their control infrastructure require expertise from various domains of semiconductor technology. In an industrial manufacturing environment, the design of qubit arrays will hence strongly benefit from defining clear specifications for various design parameters. Here, researchers employ a suite of Multiphysics simulation techniques to model Si/SiGe qubit devices and correlate them to experimental results to define parameter specifications for the qubits and for the devices hosting them. These include qubit related parameters such as qubit frequency, Rabi frequency, exchange coupling & spin coherence times – along with device parameters such as device potential uniformity, magnetic field gradients, isotopic purification, crosstalk, charge-noise and defect density. These specifications will be used to design the next generation spin qubit arrays at Intel.
Design of an Intel Quantum Control Processor for Quantum Computers
Presenter: Andrew Risinger
Quantum Computers are growing in scale, which means that the control requirements are also growing. Qubit control electronics are commonly used and discussed, but this talk introduces the Quantum Control Processor (QCP), which is responsible for orchestrating the control electronics using inspiration from classical CPU design. The QCP interprets Quantum Instruction Set Architecture (QISA) binary instructions (an extension of standard CPU instructions) into low-level control signals that are distributed to analog signal generators. The QCP will allow scalable control of a quantum processor by enabling: addressing large numbers of qubits, automatic gate recalibration, error correction & logical qubit operation and distributed processing for hybrid quantum algorithms. In this talk, researchers discuss the key design considerations and elements of the QCP and the QISA.
High-fidelity Operation of Encoded Spin Qubits on Intel Tunnel Falls
Presenter: Felix F Borjans
Quantum computers executing complex algorithms with stable logical qubits will require large numbers of highly coherent physical qubits in concert with precise pulse control. Silicon quantum dot based qubits provide both the foundation for high-fidelity qubits, and the ability to leverage the proven scalability and reliability of semiconductor manufacturing over the past decades. In fact, multiple spin-qubit encodings are available as promising candidates to form the cornerstone of scalable quantum computation in Silicon. High throughput characterizations and advanced EUV fabrication on the Intel 300mm fabrication line used for next generation processors have led to the development of the newly released Intel Tunnel Falls quantum chip available to research groups in the community, which lends itself to exploring different qubit encodings on devices with up to 12 quantum dots. The Exchange-Only (EO) encoding is one of them, allowing for complete qubit control with only baseband pulses. Here, researchers present the first results on high-fidelity spin qubit control based on the EO encoding, as well as continued progress in high-fidelity operation of single-spin qubits.
Presenter: Kevin Rasch
The Intel Quantum SDK uses quantum extensions to C++ to describe circuit-based quantum-hybrid algorithms. To go beyond basic circuit-level descriptions, the Functional Language Extension for Quantum (FLEQ) has been recently added to the Intel Quantum SDK to facilitate higher-level and extensible development of quantum algorithms, with which complex circuits can be built at compile time using a modular functional design. In this talk, researchers introduce a toy example of a quantum domain-specific language implemented using FLEQ in such a way that no circuit description is required, but rather only domain-specific knowledge of the problem.
High Volume Characterization Techniques for Industry Manufactured Si/SiGe Spin Qubit Devices
Presenter: Samuel Neyens
As spin qubit devices advance in size and complexity, improvements in component yield and process variation will be increasingly necessary to obtain high performance devices. Towards this end, high volume cryogenic measurement will be critical both to optimize fabrication processes as well as to identify the highest performing devices to package in a quantum computing stack. In this talk researchers review measurement techniques from the Intel Quantum Hardware group to characterize industry manufactured spin qubit devices with a 300 mm cryogenic wafer prober at 1.6 K. Researchers present the latest high-volume data on Intel's spin qubit process and demonstrate how advances in spin qubit component yield combined with a low disorder Si/SiGe host material lead to a high success rate for spin qubit applications.
Presenter: Daniel Keith
Electron spin qubits hosted in quantum dots are a promising platform for quantum computing as they are dense, coherent, and can be integrated with advanced semiconductor manufacturing. A key challenge is achieving sufficient uniformity in these devices to scale to larger arrays as the properties of quantum dots can be influenced by many aspects of the solid-state environment such as disorder or the atomistic details of interfaces. Important to this task is to find fast and reliable methods to measure and build statistics across many quantum dots and devices, allowing the comparison of different integration processes and materials different integration processes and materials. Here researchers detail the measurement infrastructure and techniques used to measure disorder and extract valley and orbital splittings, charge noise, exchange tunability, and coherence over multiple devices and wafers fabricated at Intel.
Introducing Hardware Awareness to PCOAST Synthesis
Presenter: Albert T Schmitz
The Pauli-based Circuit Optimization Analysis and Synthesis Toolchain (PCOAST) was recently introduced as a method for the optimization of quantum circuits and implemented as the primary optimization method in the Intel® Quantum Software Development Kit. Though PCOAST includes optimizations on the PCOAST graph representation, the highly efficient outcomes are primarily due to the PCOAST circuit synthesis of the graph. However, PCOAST synthesis as originally introduced is agnostic to hardware constraints such as limited connectivity or faulty gates. This work discusses the extension of PCOAST synthesis to include constraints by extending the definitions of the synthesis search functions. Researchers adapt common graph-based data structures to choose among the limited set of two-qubit gates when they are generated. This avoids costly SWAPs by leveraging a better realization of arbitrary Pauli operator nodes in the context of the whole circuit as well as the hardware. Researchers also argue that the algorithmic complexity of hardware awareness is on par with PCOAST synthesis without it.
Introduction to the Intel Quantum SDK Version 1.1
Presenter: Xin-Chuan Wu
The Intel Quantum SDK is a comprehensive platform that enables developers to craft applications on a full-stack system integrated with an LLVM-based industry standard compiler, which offers user-friendly C++ extensions for the construction and optimization of quantum circuits. This SDK provides dynamic quantum instructions to perform the execution of hybrid quantum-classical applications. The recent version 1.1 introduces a tensor network simulator and a Clifford simulator, broadening its applicability in quantum algorithm development. Additionally, a custom backend wrapper has been unveiled, allowing users to link their distinct quantum backend with the SDK. The compiler optimization passes have been made open source, granting all users the capability to design and contribute their own optimization processes. The Intel Quantum SDK v1.1, with its adaptability in creating custom compiler passes and quantum backends, serves as an invaluable resource for researchers pushing the boundaries of quantum computing.
Quantum Error Correction Modeling using the Intel® Quantum Software Development Kit (SDK)
Presenter: Anne Matsuura
A common use for quantum simulation is the evaluation and vetting of quantum error correction (QEC) protocols. This talk provides an example of the use of the full-stack-in-simulation capabilities of the Intel Quantum SDK for this purpose. Researchers start by demonstrating scaling simulations using a Clifford simulation backend to investigate the existence of an error threshold. Due to the hybrid design of the Intel Quantum SDK, researchers show how the classical decoding implementation can be written in C++ and seamlessly integrated with the quantum syndrome extraction circuit. Researchers will also demonstrate the simulation of smaller code instances with more realistic simulation modeling. This is done through tomography on a full-stack simulation to extract chi matrix representations of the gates. These chi matrices are then fed into the custom error modeling interface for the Intel Quantum Simulator state vector qubit backend to scale to code sizes of near-term interest.
Readout of Spin Qubit Arrays Made by Advanced Semiconductor Manufacturing
Presenter: Simon Schaal
Silicon-based quantum processors can leverage advanced semiconductor processing, offering a promising path to the large qubit count required for reaching computational advantage. High-fidelity quantum state readout is a core element of a quantum processor and requires carefully designed cryogenic readout circuits and has been demonstrated using both cryo-amplifier circuits and radio-frequency reflectometry techniques. This talk addresses Intel’s current approach for readout of our 12-quantum dot array Tunnel Falls chip with onboard HBT-based cryo-amplifiers enabling high-fidelity Pauli-spin-blockade readout. Researchers then detail progress towards scaling and improving readout to larger arrays and benchmarking different readout approaches.
Co-authored Papers
Coherent Electron Spin Shuttling in an Industrially-Manufactured Si/SiGe Triple Quantum Dot Device
In collaboration with Sandia National Laboratories
Electron spin-based qubits in silicon quantum dots (QDs) are a promising platform for quantum information processing thanks to their long coherence times and the availability of mature silicon microelectronics fabrication techniques. An open challenge in the field is to determine the best mechanism for transporting quantum information over long length scales, a feature that will likely be needed in future implementations to facilitate coherent links between distant qubits. One potential path to achieving a stable long-ranged interaction is to use coherent spin shuttling through an array of quantum dots. This work demonstrates coherent shuttling of an electron spin in an isotopically enriched, industrially-manufactured Si/SiGe triple-QD device. Researchers operate an encoded two-electron singlet-triplet qubit to characterize the transferability of an electron between neighboring QD sites while maintaining the coherence of the entangled two-electron spin state. The results are encouraging steps towards achieving shuttling-based long-ranged entanglement in semiconductor spin qubit device.
Characterization of Multiple Qubit Encodings in Industrially-Manufactured Silicon Quantum Dots
In collaboration with Sandia National Laboratories
Silicon-based spin qubits in lithographically defined quantum dots (QDs) are a promising platform for quantum computing due to their ability to use established silicon growth and processing technologies. These devices are operated using a variety of different qubit encodings that may have distinct advantages and disadvantages. This work explores two encodings that utilize baseband pulsing techniques to provide localized control of single qubits. The singlet-triplet encoding requires two electrons and two QDs with universal single-qubit control accomplished by evolution of the state in the presence of a magnetic field gradient between electron spins and the exchange interaction. In contrast, the exchange-only encoding provides universal single-qubit control through only the modulation of the exchange interaction, at the cost of requiring three electrons and three QDs and introducing additional leakage states. This research presents experimental realizations of both encodings in a single isotopically enriched, industrially-manufactured Si/SiGe quantum device. Researchers characterize and compare the operation of the different encodings to weigh their advantages and disadvantages for quantum computation.
Scott Bair is a Senior Technical Creative Director for Intel Labs, chartered with growing awareness for Intel’s leading-edge research activities, like AI, Neuromorphic Computing and Quantum Computing. Scott is responsible for driving marketing strategy, messaging, and asset creation for Intel Labs and its joint-research activities. In addition to his work at Intel, he has a passion for audio technology and is an active father of 5 children.
Scott has over 23 years of experience in the computing industry bringing new products and technology to market. During his 15 years at Intel, he has worked in a variety of roles from R&D, architecture, strategic planning, product marketing, and technology evangelism. Scott has an undergraduate degree in Electrical and Computer Engineering and a Masters of Business Administration from Brigham Young University.
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