Intel Unveils PowerVia Technology Among Seven Papers at VLSI 2023

Scott Bair is a key voice at Intel Labs, sharing insights into innovative research for inventing tomorrow’s technology.

Highlights:

• The 2023 Symposium on VLSI Technology and Circuits will run from June 11th through 16th in Kyoto, Japan.
• Intel was invited to discuss its implementation of backside power, PowerVia, in a product-like chip: an industry-leading advancement resulting in over 90% cell utilization.
• Intel’s other contributions include applications of 2D materials in the Back End of Line, a 256 Gb/s 3D-integrated silicon photonic receiver suitable for integration in XPU/switch packages, and an all-digital voltage droop monitor with coupled ring-oscillators for accurate in-situ droop monitoring every clock cycle.

The 2023 Symposium on VLSI Technology and Circuits will run from June 11th through 16th in Kyoto, Japan. Focused on “rebooting technology and circuits,” the conference promises novel avenues for a sustainable future. Intel is proud to contribute seven works at this year’s symposium; four of which detail technology innovations, and three detail circuit innovations. Most notably, Intel was invited to discuss its implementation of backside power in a product-like chip: an industry-leading advancement resulting in over 90% cell utilization. 

Intel recently announced its decoupled development of PowerVia which will be introduced on the Intel 20A process node in 2024. This power delivery solution addresses the growing issue of interconnect bottlenecks in area scaling by moving power routing to the backside of a wafer. After fabrication and testing on a silicon test chip, PowerVia was confirmed to bring a remarkably efficient use of chip resources, enabling chip designers to increase transistor density without sacrificing resources to deliver more power and performance than ever. Across two additional papers, Intel researchers will present PowerVia implemented on Intel 4 finFET process as well as pre- and post-silicon findings from implementing an Intel E-Core in PowerVia technology.

Intel’s other contributions include applications of 2D materials in the Back End of Line, a 256 Gb/s 3D-integrated silicon photonic receiver suitable for integration in XPU/switch packages, and an all-digital voltage droop monitor with coupled ring-oscillators for accurate in-situ droop monitoring every clock cycle.

Technology Contributions

[T1-1] E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology

PowerVia Technology is a novel innovation to extend Moore’s Law scaling by having Power Delivery on the backside. This paper presents the pre & post-silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of > 90% in large areas of the core while showing > 5% Frequency benefit in Silicon due to reduced IR drop. Successful Post-Silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristic of the PowerVia test-chip is in line with higher power densities expected from logic scaling.

[T6-1] Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing

This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with >90% cell utilization showed >30% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.

[T14-3] 2D Materials in the BEOL

2D materials, such as Transition Metal Dichalcogenides (TMDs), have potential for large impact in future technologies due to their inherent atomic thickness. Here, we present multiple applications of 2D materials in the Back End of Line (BEOL). First, we report various 300 mm BEOL compatible growth methods for 2D materials. We reveal the ultra-scaling of interconnect barriers with a 10 Å 2D BEOL barrier yielding comparable performance to 25 Å Tantalum (Ta). Furthermore, we present a novel BEOL passivation technique for an unstable film by encapsulating it with a 2D material. Lastly, with a 300 mm BEOL grown WSe2 film, we report appreciable PMOS currents up to 15 μA/μm for future BEOL CMOS technologies.

[TFS2-1] Novel Cell Architecture with Back-side Transistor Contacts for Scaling and Performance

The introduction of PowerVia increases the efficiency of power delivery by adding back-side interconnects and improves performance of front-side interconnects by relaxing the minimum pitch needed, and by enabling optimization for signaling. Addition of back-side transistor contacts further decreases cell area and increases performance. In this paper, we present an experimental demonstration of a novel cell architecture with back-side device contacts and back side power delivery.

Circuit Contributions

[C6-2] A 256 Gbps Heterogeneously Integrated Silicon Photonic Microring-based DWDM Receiver Suitable for In-Package Optical I/O

We present a 256 Gb/s 3D-integrated silicon photonic (SiPh) receiver suitable for integration in XPU/switch packages. The photonic IC (PIC) integrates a multi-wavelength laser, optical amplifier, and cascaded micro-ring resonators (MRRs) to implement dense wavelength division multiplexing (DWDM) with minimal footprint. The 28nm CMOS electronic IC includes eight SerDes channels, and PIC interface/control electronics. A dither-based thermal control unit tunes MRRs in the optical demux to align with the laser grid with sub-pm resolution. Measured results demonstrate BER<1e-12 when receiving 256 Gb/s DWDM input generated by MRRs modulating eight 200 GHz-spaced wavelengths. This is 2X higher aggregate bandwidth than previously published SiPh MRR-based receivers, with higher level of photonic integration.

[C12-2] 218Kauth/s, 3nJ/auth SCA/ML-Resistant Privacy-Preserving Mutual Authentication Accelerator with a Crypto-Double-Coupled PUF in 4nm class CMOS

A SCA/ML-resistant secure PPMA accelerator is fabricated in 4nm class CMOS, occupying 3776μm2. Double-coupled crypto microarchitecture using a 128b strong PUF along with AES- 128 round hardware achieves CRP space of 1028 with BER of 0.15%. Secure mote/server-authentication throughput of 218/435Kauth/s is demonstrated with no side-channel leakage detected after 2.5M authentications. Resistance to machine learning attacks is demonstrated against 10M training CRPs.

[C25-2] A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS

We present an all-digital voltage droop monitor (VDM) with coupled ring-oscillators (CoRO) for accurate in-situ droop monitoring every clock cycle. Measurements from a 3.2mm2 testchip in Intel 4 CMOS containing 9 3-way CoRO and baseline RO VDMs demonstrate 3X improvement in CoRO resolution (~2.6mV/b) over the baseline. In addition, measurements show 3 uncertainty (repeatability) error of CoRO VDM (+/-9mV) is ~25% lower than the baseline. The overall droop detection error improvements achieved by CoRO VDM are 12mV, 15mV and 17mV, respectively, depending on the type of calibration used – per instance/temperature/die, per temperature/die, or per die. This corresponds to associated IP power savings of 2.9%, 3.2% and 3.7% during functional use.