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What’s in store for the latest RISC-V development board

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When a technology is hyped as “inevitable” and “without limits,” expectations are high. 

Enter the HiFive Pro P550 chip, aka Horse Creek, touted as the highest development board on the market.

This general purpose development board will be available to the RISC-V community to buy, use, and develop software for. Release is scheduled for the summer of 2023, you can sign up for notifications here or see an overview of all the specs here.

Sam Grove of SiFive* and Nikhil Krishna Gopalakrishna from Intel gave a sneak peek at the development board, features, capabilities and what's inside the system-on-chip (SoC) at the recent RISC-V Summit.

First up:  A look into the “soul of the machine:”

  • SiFive Performance P500 Series Quad-Core CPU RISC-V RV64GBC ISA 
  • Private L2, Shared L3, Streaming Prefetcher 
  • SiFive Insight Debug and Trace 
  • 2+ GHz CPU Frequency Intel 4 Process 

Target uses:

  • RISC-V Software Ecosystem
  • Mass Market Availability 
  • Premium Software Development Board 
  • RISC-V Build / Test / Deploy Servers 
  • Developer Desktops 
  • RISC-V Rack System 

 

soul.png

“This is going to push RISC-V software development to new levels, new heights,” Grove says. ”This is really for people building software, packaging software and distributing software to the rest of the ecosystem.”

It can fit into a developer desktop or a RISC-V rack system so you can develop locally and natively or hook it up to your continuous integration and continuous delivery (CI/CD) or continuous testing (CT)  systems in the cloud.

Zooming out,  for a look at a high-level block diagram of the architecture of the board, it’ll fit into a microATX with the Intel Horse Creek SoC “at the heart of it” fitted out with 16 gigabytes of DDR5 memory and a PCIe* switch for expansion. That expansion is allows for more connectability, for more cards — enabling drivers for the M.2 key slots important for Wi-Fi networking or Non-Volatile Memory Express (NVME)-based storage and USB 3 for more expansion and on-board graphics and networking.

SoC: The specs

“When we first looked at this opportunity with RISC-V, our first thought was: Let's put ourselves in the shoes of the developer. What do they need to develop software?” Gopalakrishna says. “The core is fantastic, now let's bring together the most important peripherals around it to enable good ecosystem development.

Here’s what that looks like:

  • Intel 4 Process
  • 4mm x 4mm monolithic die
  • 19x19 standard FBGA package
  • Intel DDR5-5600 Hard IP PhV
  • interfaced with Cadence* DDR5
  • Controller IP
  • Intel PCIe* Gen5 Hard IP PhV interfaced with Synopsys* PCle*
  • Controller IP - supports 8 lanes
  • 2 MB Shared Scratchpad memory
  • Other common SoC peripheral support

A Look at PCIe* Features

features.png

 

What features does PCIe* enable?  It's a Gen 5 root complex it can go up to 32 GTS, we support up to eight Lanes of course at Gen 5 that probably will be supporting about four lanes or two lanes but at Gen 3 it can do eight. “We support all the configuration transactions, we can go full payload from 128 to four kilobytes, and auto-lane reversal that we are actively using on the board,” Gopalakrishna explains. 

One unique feature? "The fight training sequence is automatically managed by embedded firmware —  there’s no involvement from the user to train the either the PCIe5* or the DDR5*,” he adds. “We’re also bringing in new capabilities for RASDES for debugging of PCIe.”

Horse Creek Boot Flow 

Next up is a very high-level look into how Horse Creek boots up: It starts with dedicated boot ROM, boots up and passes control to the secondary bootloader, that bootloader jumps to the Linux* kernel and finally brings up the operating system. 

The speakers called the performance “breakthrough,” compared to the previous SiFive chip: “Based on feedback from the community and developers who depend on these to build the RISC-V packages, is that they’re seeing the that performance compared to HighFIve Unmatched is a three-plus uplift in SPECint,” Grove says.  “As for the memory subsystem in the caching, we're seeing greater than 20 times increases on Libquantum which is really like a memory-streaming type benchmark. “What this means is you can build more you can develop more, you can package more and you can ship more."

The upcoming chip is the latest stop on a journey that began in 2016 with HiFive 1, a microcontroller baseboard that enabled FreeRTOS* and other microcontroller real-time operating system (RTOS). Then came HiFive Unleashed*, the first Linux-capable board, Debian* came online followed by HiFive Unmatched* which brought support from Canonical* and Ubuntu*, Fedora* and many others.

 

Check out the 10-minute presentation on YouTube. 

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