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Modularity and Standardization Transforming Server Architecture

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Rapid digital transformation has ignited an eruption of intelligent devices and cloud-based services accelerating OEMs’, Hyperscalers’ and Cloud Service Providers’ need to offer more compute choices faster.  However, constrained budgets, increasing costs and growing environmental impact are motivating suppliers to search for a new way to meet these conflicting requirements. 

Modular server architectures provide the answer to the fundamental change essential to address these market, business, and ecological conditions. They let suppliers use standard building blocks, flexibly configure systems and deliver innovative solutions.  

In early 2022, six companies, Intel, Dell, HPE, Google, Meta, and Microsoft (and recent addition AMD) kicked off a collaboration in the Open Compute Project (OCP) called Data Center Modular Hardware System (DC-MHS).   Through six base specifications, DC-MHS documents several types of Host Processor Modules (HPMs) and how they interface with building blocks needed to configure a full server. Host Processor Modules (with CPU and memory) and other modular, standardized elements allow customers to offer a wider range of systems for Enterprise, Hyperscale, Cloud, Telecom and Edge sooner and with reduced engineering investment. The same module is deployed in multiple configurations at higher scale. 


M-FLW (Modular Hardware System FulL Width)
M-DNO (Modular Hardware System Partial Width Density Optimized)
M-CRPS (Modular Hardware System Common Redundant Power Supply)
M-PIC (Modular Hardware System Platform Infrastructure Connectivity)
M-XIO (Modular Hardware System EXtensible I/O)
M-PESTI (Modular Hardware System PEripheral Sideband Tunneling Interface)

OCP DC-SCM r2 (Datacenter Secure Control Module)
OCP NIC r3 (Network Interface Card)

Figure 1 – Demonstrating DC-MHS ModularityFigure 1 – Demonstrating DC-MHS Modularity

Figure 1 represents how a single socket Density Optimized Host Processor module, combined with standard building blocks, may be designed in three different solutions.    

Key benefits of an OCP DC-MHS modular design include:

  • Reduced development, integration, and validation costs shared between CPU and Platform Suppliers
  • Reduced number of grounds up custom designs, only smaller changes for Bill of Materials and Design for Manufacturing
  • Reusable building blocks across multiple designs in multiple markets leading to economies of scale with higher volume shared across the industry
  • Faster time to market versus ground up custom design
  • ODMs’ specification-compliant “calling card” that they can shop among multiple Tier 1 customers
  • Consume more from “CPU suppliers”, like Intel, including HPM optimization points, which mean the OEMs and ODMs require less engineering work
  • Future proof design that spans multiple generations, potentially requiring only a Host Processor Module replacement in the product configurations
  • Sustainability:  server elements can be re-used or recycled, reducing material waste and contributing to improved sustainability critical to the environment.

OCP’s DC-MHS lays a new foundation for modular server architectures.  Kickstart your solutions today with two Intel Reference Designs (including schematics and layout board files):  1) A single socket Xeon Modular-Density Optimized Host Platform Module targeted to applications like vRAN, SASE, Media and 1S optimized Enterprise servers and 2) A two-socket Xeon Modular Full Width Host Platform Module for Enterprise, Cloud and Hyperscale markets.  

Video demonstration of DC-MHS:

Both Reference Designs available on Intel Resource and Design Center are compliant to the six OCP DC-MHS specifications.  Links to the collateral:  Single Socket DC-MHS design, Two socket DC-MHS design.  If unable to access, please contact your Intel sales representative.

For more information, check out the replay of Intel’s OCP Global Summit Keynote “Reimagining the Data Center” on October 17, 2022 and download the six OCP DC-MHS v1.0 specifications.  

About the Author
Principal Engineer Platform Hardware Pathfinding in Data Platforms Engineering and Architecture (Intel Xeon)