I210 PCIe Input Clock (PECLK)

[dbourget]

I would like to know what should be the parallel termination resistor for the PECLK inputs. My board includes 50ohm parallel termination (one resistor on each polarity) to the ground but the signal amplitude is 2x higher than expected.

[Caguicla_Intel]

Hello dbourget,

Thank you for posting in Intel Ethernet Communities. 

Can you share if this is your own designed motherboard? If no, kindly indicate the brand and model of your motherboard. Please also provide more information about your setup/environment for us to determine which department would be best to assist you.

Looking forward to hear from you. 

Shoule there be no response, I will make a follow up after 3 business days. 

Best regards,

Crisselle C

Intel® Customer Support

[dbourget]

Hi Crisselle

You will find attached our design for the Refclk. I made a test by replacing the 50ohm parallel termination by a 25ohm and the Refclk amplitude seems closer to the recommended amplitude of the PCIe specifications. I'm wondering what is the impendance of the PECLK input.

Best Regards

[Caguicla_Intel]

Hello dbourget,

Appreciate your swift response.

Can you confirm that you are designing your own board and the I210 is embedded to it? Once we have your confirmation, we will move this request to the concerned team to assist you further.

If no, please visit the link below and confirm if the information you are looking for is here so we can check further? 

Page 24 Section 2.3.1 and page 801 section 12.1.2

https://cdrdv2.intel.com/v1/dl/getContent/333016

Awaiting to your reply.

In case we don't hear from you, I will make a follow up after 3 business days. 

Best regards,

Crisselle C

Intel® Customer Support

[dbourget]

Yes, we are designing your own board and the I210 is embedded to it.

[Caguicla_Intel]

Hello dbourget,

Thank you for the reply. 

Please be informed that your query will be best answered by our Embedded Connectivity Support team. We will help you to move this post to the designated team for further assistance. Please feel free to contact us if you need assistance from Ethernet support team.

May you have a good day!

Best regards,

Crisselle C

Intel® Customer Support

[CarlosAM_INTEL]

Hello, @dbourget:

Thank you for contacting Intel Embedded Community.

You should review that your implementation fulfills the requirements stated in the Intel® Ethernet Controller I210-CS Checklist document # 569653. You can find it when you are logged into your Resource and Design Center (RDC) privileged account on the following website:

https://cdrdv2.intel.com/v1/dl/getContent/569653

You should fill out the form stated on the following website when you have problems with the provided website or want to update your RDC account:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

[dbourget]

Hello Carlos,

Could you please help me to get access to the document #569653.

I sent and received many emails regarding the privileged account and still not able to acces this document.

I only want to know want should be the parallel termination resistance at the input of the PECLK signal.

Best Regards

[SLabe]

Hi Carlos, I'm the Arrow FAE assisting Dany with this... Upon reviewing the Layout checklist for the i210, all it states for the PCLK is the following:

Connect PECLKn(25) and PECLKp(26) to the 100 MHz PCIe system clock.

No mention of termination or coupling requirements... So is it safe to assume none are required and a point to point connection to the clock source is correct?

Thank you

[CarlosAM_INTEL]

Hello, @SLabe:

Thank you for contacting Intel Embedded Community.

You should follow the guidelines and suggestions stated in the documentation because they have been tested and validated by Intel. However, in case you want to implement something out of the documented recommendations, you should test and validate them on your own.

Best regards,

@CarlosAM_INTEL.

[SLabe]

Agreed. In this case I believe one must follow HSCL termination guidelines set forth by the clock source.

Thank you Carlos,