Intel 82580 PCIe reference clock termination

[DMau]

Hi,

I have a single board including both PCIe reference clock generator (Abracon AB-557-03) and Intel 82580 ethernet controller.

In this configuration without add-in card, is it a best practice to add 100 ohms termination resistor close to the 82580 input (PE_CLK) ?

Is there internal termination resistor configurable by one of the 82580 registers ?

Best regards,

David

[Mike_Intel]

Hello David,

Thank you for posting in Intel Ethernet Communities. 

Regarding your inquiry, you may contact the manufacturer of the motherboard since you are using an on-board NIC.

At the same time, I will a also route this thread to our embedded team for them to further assist you.

If you have questions, please let us know.

Best regards,

Michael L.

Intel Customer Support Technicians

A Contingent Worker at Intel

[DMau]

Hello Michael,

Thanks for your support.

We are the motherboard manufacturer. We looked at the 82580 reference design and there is no termination.

The question is do we add terminaison depending on the distance between our clock generator and the 82580 reference clock input to improve if needed the signal integrity.

Is there an integrated terminaison inside the 82580 - fixed or configurable by software ?

Best regards,

David

[CarlosAM_INTEL]

Hello, @DMau​:

Thank you for contacting Intel Embedded Community.

Could you please list the sources used to design the units related to your questions, also if it has been verified by Intel?

We are waiting for your clarification.

Best regards,

@Mæcenas_INTEL​.

[DMau]

Hello Maecenas,

Here are the documents:

• 82580 REFERENCE DESIGN (schematic), doc.number 322445-006EN, rev.2.1 2010-04-02
• Intel® 82580EB/82580DB Gigabit Ethernet Controller Datasheet, revision 2.5 October 2011
• Intel® 82580EB/82580DB Gigabit Ethernet Controller Datasheet, revision 2.6 August 2015
• PCI Express ®  Card Electromechanical Specification Revision 2.0 , April 11, 2007

Our design has not been verified by Intel.

Thanks and best regards,

David

[CarlosAM_INTEL]

Hello, @DMau​:

Thanks for your reply.

Your implementation can be verified by Intel if you follow the steps stated at:

https://edc.intel.com/Tools/Design-Review/Default.aspx

Best regards,

@Mæcenas_INTEL​.