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i210 internal PHY 1000BASE-T autoneg

cgao
Beginner
245 Views
hello,  I use i210 internal PHY in our  designed embeded system board,the internal PHY can  auto negotiate normally with 10Mbs/100Mbs Full/Half duplex. 1000Mbs full duplex cannot be auto negotiated whatever I set to auto-nego or 1G full-duplex forced at PC which connected to designed embeded system board by CAT 6,at the end it will show 100Mbs in PC network and share center. I've tryed  iNVM , FLASH and manually config PHY without both of them as below:     /* PHY init IGP 3 */     /* Enable rise/fall, 10-mode work in class-A */     hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);     /* Remove all caps from Replica path filter */     hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);     /* Bias trimming for ADC, AFE and Driver (Default) */     hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);     /* Increase Hybrid poly bias */     hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);     /* Add 4% to Tx amplitude in Gig mode */     hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);     /* Disable trimming (TTT) */     hw->phy.ops.write_reg(hw, 0x2011, 0x0000);     /* Poly DC correction to 94.6% + 2% for all channels */     hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);     /* ABS DC correction to 95.9% */     hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);     /* BG temp curve trim */     hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);     /* Increasing ADC OPAMP stage 1 currents to max */     hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);     /* Force 1000 ( required for enabling PHY regs configuration) */     hw->phy.ops.write_reg(hw, 0x0000, 0x0140);     /* Set upd_freq to 6 */     hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);     /* Disable NPDFE */     hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);     /* Disable adaptive fixed FFE (Default) */     hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);     /* Enable FFE hysteresis */     hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);     /* Fixed FFE for short cable lengths */     hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);     /* Fixed FFE for medium cable lengths */     hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);     /* Fixed FFE for long cable lengths */     hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);     /* Enable Adaptive Clip Threshold */     hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);     /* AHT reset limit to 1 */     hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);     /* Set AHT master delay to 127 msec */     hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);     /* Set scan bits for AHT */     hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);     /* Set AHT Preset bits */     hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);     /* Change integ_factor of channel A to 3 */     hw->phy.ops.write_reg(hw, 0x1895, 0x0003);     /* Change prop_factor of channels BCD to 8 */     hw->phy.ops.write_reg(hw, 0x1796, 0x0008);     /* Change cg_icount + enable integbp for channels BCD */     hw->phy.ops.write_reg(hw, 0x1798, 0xD008);     /* Change cg_icount + enable integbp + change prop_factor_master      * to 8 for channel A      */     hw->phy.ops.write_reg(hw, 0x1898, 0xD918);     /* Disable AHT in Slave mode on channel A */     hw->phy.ops.write_reg(hw, 0x187A, 0x0800);     /* Enable LPLU and disable AN to 1000 in non-D0a states,      * Enable SPD+B2B      */     hw->phy.ops.write_reg(hw, 0x0019, 0x008D);     /* Enable restart AN on an1000_dis change */     hw->phy.ops.write_reg(hw, 0x001B, 0x2080);     /* Enable wh_fifo read clock in 10/100 modes */     hw->phy.ops.write_reg(hw, 0x0014, 0x0045);     /* Restart AN, Speed selection is 1000 */     hw->phy.ops.write_reg(hw, 0x0000, 0x1340); above config is  for PHY ID :0x02A80391 which i copyed from igb source code  ,actually  PHY ID is 0x01410C00  in PHY identify 1&2(Reg:2&3) cause I have no idea for this problem after trying throusand routes. Does someone know what the issue could be? Thanks a lot.
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2 Replies
Mike_Intel
Moderator
228 Views

Hello cgao,


Thank you for posting in Intel Ethernet Communities. 


Base on your inquiry, we have specific forum for these issues and I will be transferring this thread for faster response. 


Thank you.


Best regards,

Michael L.

Intel® Customer Support Technician


CarlosAM_INTEL
Moderator
202 Views

Hello, @cgao:

Thank you for contacting Intel Embedded Community.

Could you please confirm that this thread has been addressed to us in the forum stated on the following website?

https://community.intel.com/t5/Embedded-Connectivity/i210-internal-PHY-cannot-auto-neg-1000Mbs/m-p/1...

In case that your answer is affirmative, you should follow the suggestions provided.

Best regards,

@CarlosAM_INTEL.

 

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