I am working with a Haswell CPU: CL8064701483802 SR17L and PCH: DH82QM87
Problem: After a power-off scenario the system seems to start to power on normally but after plt_rst has been released initially it is asserted once again for 5ms. The input scenario that brings this extra reset out seems to be mostly random. We have some boards that I cannot get this reset to ever occur, and a couple of boards that I can fairly consistently produce this extra reset. S3 and S4 do not assert during these resets, S5 and SUS_STAT seem to toggle during these short resets (I’m unsure at this time if this is because of how they may be configured through the BIOS or not).
What I found in the PCH documentation that caught my attention is a mention to the INIT# going active as well as the RCIN pin. Currently our RCIN pin is tied directly (through a 10k resistor) to the 3.3V ATX power rail. This was derived from the reference schematic. Mentions of the RCIN say that “To prevent a 2nd reset due to the same RCIN# assertion, RCIN# must de-assert prior to PLTRST# de-assertion”. It also says “RCIN# signal is expected to be low during S3, S4, and S5 states. Transition on the RCIN# signal in those states (or the transition to those states) may not necessarily cause the INIT# signal to be generated to the processor”.
My question to you is whether or not you know what this second reset during a cold boot could be triggered by, and why it doesn’t seem to consistently trigger across different boards. Any guidance that you can give me at this time will be greatly appreciated.
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You need to review the reset information stated in section 14, on pages 395 through 404 of the Intel® Xeon® Processor E5/E7 v3 Product Family External Design Specification (EDS), Volume One: Architecture Volume 1 of 3 document # 507851, which may help you. You need to be logged into your Resource & Design Center (RDC) privileged account to find the user guide and this tool on the following website:
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