We followed Intel CRB 572383 to connect SOC VCCIOA with VNN power on our LPDDR4 platform
, but another Intel CRB (561529) said VCCIOA should be connected
to VDDQ for LPDDR4 memory , we would like to know if it will impact boot up ,
Our platform is hang on post code 2E when power on ( memory initial ).
Hello, IJ :
Thank you for contacting Intel Embedded Community.
In order to be on the same page, could you please give us the SKUs and part numbers of the processors related to your questions?
Could you please let us if the affected design has been developed by you or a third-party company? In case that it is third-party design, please let us know all the information related to it.
In case that it has been designed by you, could you please let us the sources that you have used to develop it? Also, could you please clarify us if your design has been reviewed by Intel?
Waiting for your answers to these questions.
Hello, IJ :
Thanks for your reply.
The information that may help you is stated in section 188.8.131.52, on page 67 of the https://cdrdv2.intel.com/v1/dl/getContent/557775 Intel(R) Pentium(R) and Celeron(R) Processor N- and J- Series (Formerly Apollo Lake) Design Guide document # 557775.
This PDG is accessible when you are logged into your Resource & Design Center (RDC) privileged account that should be requested by filling out the https://www.intel.com/content/www/us/en/forms/design/contact-support.html RDC Account Support form.
We hope that this information may help you.