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KYang11
Beginner
610 Views

Apollo lake- From G3 to S5 the

When we set the "Afer G3 status" to "S5" in the BIOS. The system will hold and wait the power button in next power on from G3. But I measured the SLP_S3-L which will output high level glitch during the G3 to S5. It is abnormal. Have any documentation for this issue?

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8 Replies
Oscar_A_Intel1
Employee
121 Views

Hello KYang11, Thank you for posting on the Intel Community. I will transferred this thread to the Embedded Community for the appropriate support. Also, please visit the Intel Resource & Design Center for Technical Resources for Designers, Engineers, and Developers. https://www.intel.com/content/www/us/en/design/resource-design-center.html Regards, Oscar A. Intel Customer Support Technician Under Contract to Intel Corporation
CarlosAM_INTEL
Moderator
121 Views

Hello, @KYang11​:

 

Thank you for contacting Intel Embedded Community.

 

Could you please clarify if the design related to this forum has been developed by you or by a third-party manufacturer?

 

In case that it is a third-party one, please provide the model, part number, and where is stated its documentation.

 

Best regards,

@Mæcenas_INTEL​.

KYang11
Beginner
121 Views

It was developed by me. My customer was confused why the power LED has a flash from G3 to S5?

CarlosAM_INTEL
Moderator
121 Views

​Hello, @KYang11​:

 

Thanks for your clarification.

 

Could you please let us know how many units has been manufactured by you, how many are related to this situation, and the failure rate?

 

Could you please list the sources that you have used to develop the affected design?

 

Best regards,

@Mæcenas_INTEL​. 

KYang11
Beginner
121 Views

I measured two products and 1 pcs / product​. They had the same issue. The failure rate is 100%.

My customer uses the SLP_S3-L signal to turning on the ATX power supply. When the system from G3 to S5, the SLP_S3-L glitch causes the system auto power on and off.

CarlosAM_INTEL
Moderator
121 Views

Hello, @KYang11​:

 

Thanks for the provided answer to our first question and additional details related to the issue that you design is experiencing.

 

However, could you please answer the last question of our previous communication?

 

Best regards,

@Mæcenas_INTEL​.

KYang11
Beginner
121 Views

I referenced the Oxbow Hill CRB to design.

CarlosAM_INTEL
Moderator
121 Views

Hello, @KYang11​:

 

Thanks for your update.

 

We suggest send your design to be reviewed by Intel through the Design Review Services department. In order to do it, please follow the procedures stated in the following website:

 

https://edc.intel.com/Tools/Design-Review/Default.aspx

 

Best regards,

@Mæcenas_INTEL​.

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