When we set the "Afer G3 status" to "S5" in the BIOS. The system will hold and wait the power button in next power on from G3. But I measured the SLP_S3-L which will output high level glitch during the G3 to S5. It is abnormal. Have any documentation for this issue?
Thank you for contacting Intel Embedded Community.
Could you please clarify if the design related to this forum has been developed by you or by a third-party manufacturer?
In case that it is a third-party one, please provide the model, part number, and where is stated its documentation.
Thanks for your clarification.
Could you please let us know how many units has been manufactured by you, how many are related to this situation, and the failure rate?
Could you please list the sources that you have used to develop the affected design?
I measured two products and 1 pcs / product. They had the same issue. The failure rate is 100%.
My customer uses the SLP_S3-L signal to turning on the ATX power supply. When the system from G3 to S5, the SLP_S3-L glitch causes the system auto power on and off.
Thanks for your update.
We suggest send your design to be reviewed by Intel through the Design Review Services department. In order to do it, please follow the procedures stated in the following website: