We are working on the bring-up of Intel atom E3826 based board. We are following coreboot+FSP approach and facing challenges in PCIe 4 lane link-up.
The Clocking scheme is connected in common clock architecture.
The Setup is working with gen1 x1 configuration by default.
Processor is booting correctly with x1 configuration & PCIE interface is also up.
Whenever we set the Root port configuration in soft bootstraps as x1(4x1s Port 1 (x1), Port 2 (x1), Port 3 (x1), Port 4 (x1)) our board boots correctly and link is detected. But as soon as we change the configuration to x4(1x4 Port 1 (x4)) our board boots and then gets stuck in FSP itself.
But when we checked linkup status on the othwer side PCIE device linkup status then it was coming on Gen1 x 4 but booting stuck at FSP.
We have tested with enabling all 4 PCIe ports as well enabling only port1 from coreboot. The result is same. Also we have tried enabling/disabling SSC "spread spectrum clock for PCIe" from flash descriptor. Here also the result is same.
- Please let us know what are we missing here.
- It will be great if you guys can provide us the debug FSP binary blob for this baytrail platform so that we can debug more deeply.
- How to set configuration for Gen1 or Gen2 link speed in coreboot-FSP setup?
Thank you for contacting Intel Embedded Community.
Could you please confirm that your implementation fulfills with the requirements stated in the Intel(R) Firmware Support Package for Intel(R) Atom(TM) Processor E3800 Product Family: Integration Guide document # 331165? It can be found at:
We are waiting for your confirmation.
Yes, we full-fill the requirements stated in the Intel(R) Firmware Support Package for Intel(R) Atom(TM) Processor E3800 Product Family: Integration Guide document # 331165.
The booting is working fine with x1 Pcie interface. Only problem with the enabling of x4 of port 1 configuration. The link-up status is coming Up at a link speed of Gen1 X 4 but booting stuck at FSP itself.