How GPIO pins are mapped inside all four gpiochip banks.

[DŠuša]

I am working with Intel Atom E3900, and I want to test specific GPIO pins (Linux is running). I am not able to find correct offset for example GPIO_3 on line B39 and GPIO_2 on line C39. These pins are connected on header of my board. So i want to export correct pins (inside linux), change voltage value on them and verify that change with multimeter.

[CarlosAM_INTEL]

Hello, @DŠuša​:

Thank you for contacting Intel Embedded Community.

The information that may help you is stated in the second row and fifth column of the Table 2-35, on pages 55 and 56 of the Intel(R) Pentium(R) and Celeron(R) Processor N- and J- Series [Formerly Apollo Lake] External Design Specification [EDS] - Volume 1 of 3 document # 557555. This document should be available when you are logged into your Resource and Design Center (RDC) privileged account in the following website:

https://cdrdv2.intel.com/v1/dl/getContent/557555

In case that you want to update your RDC account, you should request it by filling out the form stated at:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

We hope that this information may help you.

Best regards,

@Mæcenas_INTEL​.

[DŠuša]

Hello, @Mæcenas_INTEL​ 

Thank you for fast replay. Unfortunately this document did not helped me. I will try to explain my problem more correctly.

On my Linux in folder /sys/class/gpio there are 4 banks named gpiochip267, gpiochip310, gpiochip357, gpiochip434. In one of this banks GPIO_2 and GPIO_3 are placed. Usually in documentation the offset of each pin is placed in table.

For example GPIO_47 have offset 78. In that case I just take base of fist gpiochip which is 267 and add 78 on that number. If I want to export that pin, i just use "echo 345 > export" will create a "gpio345" node for GPIO #345. When I have some GPIO pin exported than I can change it`s direction (either in or out), value (0 (low) or 1 (high)), etc.

My problem is that I need to find the value of the offset for pins GPIO_3 and GPIO_2 so I can use them and test their functionality.

Thanks in advanced

[CarlosAM_INTEL]

​Hello, @DŠuša​:

Thanks for your update.

In order to help you, could you please answer our message sent the past January 8th, 2019?

Waiting for your reply.

Best regards,

@Mæcenas_INTEL​.  

[CarlosAM_INTEL]

​Hello, @DŠuša​:

Thanks for your clarification.

Based on your previous communication, the information that may help you should be reviewed with the assistance of your BIOS vendor. It can be found in section 11, on page 143 of the Apollo Lake Platform Intel Architecture Firmware Specification (Volume 2 of 2) BIOS Specification document # 559811. It is accessible when you are logged into your RDC privileged account at the following website:

http://www.intel.com/cd/edesign/library/asmo-na/eng/559811.htm

We hope that this information may help you.

Best regards,

@Mæcenas_INTEL​. 

[Dina24]

I have similar issue with Intel Atom E39XX processor. Kinldy provide the relevant document

[CarlosAM_INTEL]

Hello @Dina24:

Thank you for contacting Intel Embedded Community.

You should review the information stated in the second row and fifth column in Table 2-35, on pages 55 and 56 of the Intel(R) Pentium(R) and Celeron(R) Processor N- and J- Series [Formerly Apollo Lake] External Design Specification [EDS] - Volume 1 of 3 document # 557555. By the way, your BIOS vendor should assist you to review the information stated in section 11, on page 143 of the Apollo Lake Platform Intel Architecture Firmware Specification (Volume 2 of 2) BIOS Specification document # 559811.

You can find these documents when you are logged into your Resource and Design Center (RDC) privileged account in the following websites:

https://cdrdv2.intel.com/v1/dl/getContent/557555

https://cdrdv2.intel.com/v1/dl/getContent/559811

Your RDC account update request should be addressed by filling out the form stated in the following website:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

This information has been provided on our previous communications of this thread.

Best regards,

@CarlosAM_INTEL.

[DŠuša]

Hello, @Mæcenas_INTEL​ 

This document helped me a lot. In section 19.6 GPIO Interrupt and Wake Capabilities it is explained in details.

Thank you for your help.

Best regards,

@DŠuša​