IBIS Model Apollo Lake E3940 for LPDDR4

[LBuga]

Hi all.

I want to simulate the interface between E3940 and LPDDR4 in Hyperlynx.

• How to include in simulation the E3940 package delay? I think it's not present in IBIS file.
• How to find the models for the different types of ODT?

Best regards.

[CarlosAM_INTEL]

Hello, @LBuga​:

Thank you for contacting Intel Embedded Community.

We suggest you as a reference review the information stated in the following website that may help you:

https://www.mentor.com/pcb/multimedia/overview/hyperlynx-support-for-ddr4-and-lpddr4-4fa81818-3406-4671-831c-2db6d6d95a7b

Best regards,

@Mæcenas_INTEL​.

[LBuga]

Hello.

Te problem is in your ibis model:

[IBIS Ver]   3.2

[File name]   bxtp_lp4_1p1v.ibs

[File rev]   1.0

[Date]     Tue Dec 30 23:07:03 2014

[Source]    INTcinIBIS vp14ww18.3

• there aren't ODT models
• there is no package delay for any pins.

How can simulate the interface with LPDDR4 without these datas?

Best regards.

[LBuga]

Hello.

Do you have any news?

Best Regards.

[GFeng]

Are there any solutions to the two questions in this thread? I am using the E3950, and have exact the same problems. The IBIS model downloaded through Intel RDC does not contain ODT models, so the reading process of the LPDDR4 can not be simulated in Hyperlynx. The package delay info is in another excel sheet, and I don't know how to put these info into the simulation. Xilinx FPGA will put all required info of the memory controller in its IBIS file. Not sure if Intel can provide something similarly?