The PCI Express motherboard uses a 24-port system interconnect switch 89HPES32NT24AG2 (hereinafter referred to as "switch") as the Slave device. If an Intel Atom E38xx processor-based module is used as the System module, there are no errors when communicating PCI Express with the slave module regardless of the "switch" mode (Common clock or Non-common clock) (PCI Express x1 Gen 1, Gen2 mode). If the module is used as the system module
on the basis of the Intel processor Atom E39xx, at data exchange on PCI Express with slave module of a mistake are absent only in an operating mode of "switch" Common clock (x1 Gen1, Gen2); when the latter is in Non-common clock mode (the PCI Express bus clock signal is used internally, not from the Intel Atom E39xx processor), then in x1 Gen 1 mode
correctable (recoverable) errors occur, at the same time the connection is repeated, in the mode Gen2 uncorrectable errors occur, which leads to impossibility execute the slave device configuration loops.
Q: What additional Atom E39xx processor settings will allow PCI Express with slave to run without errors a device that operates in Non-common clock mode?
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We want to address the following question to better understand the reported situation:
Could you please let us know if the design related to this situation has been developed by you or by a third-party company?
Could you please give us the information of the affected system (such as the manufacturer, part number, model, and where we can find its information)?
Could you please list the sources used to develop the affected system?
We are waiting for your clarification.
Thanks for the answer.
All devices (motherboard, modules based on Intel Atom E38xx processors, Atom E39xx and "switch") are in-house development modules. The devices are designed in accordance with typical schematics and recommendations of chipmakers, for example, a module based on the Intel Atom E39xx designed based on the LEAF HILL schematic rev. 2.2 (Intel document No. 561529) and External Design Specification Volume 1-4 (Intel document No. 557555-557557). The problem only occurred with the PCI Express interface in non common clock mode in the module based on the Intel Atom E39xx processor, all other interfaces work normally. Slave module ("switch") is developed based on the description of switch 89HPES32NT24AG2: https://www.renesas.com/us/en/document/dst/89hpes32nt24ag2-datasheet. By default, the switch is used in non common clock mode, where there were problems with Atom E39xx. Having made modifications on the module, the switch was put into common clock mode and the problems disappeared.
Our designs have not been verified by Intel, but I repeat, the schematics are made in strict accordance with Intel's recommended documents, the design of the circuit board topology and their manufacture in accordance with the requirements of the standards IPC-7351, IPC-2221, IPC-2222, IPC-7093, IPC-7095, IPC-6012, IPC-A-600, the quality of manufacture in accordance with the requirements of the standards IPC-A-610, J-STD-001. The described problem is manifested on several processors E39xx the last revision and has not appeared once with any processor E38xx. Changing the capacitors ratings on PCI Express transmission lines, as well as changing the known mode settings of the E39xx PCI Express controller, did not give results.
... In addition, the Non-Common Clock with SSC Mode Enable Strap mode was set in the descriptor (offset 0x130, 0x138), as well as changing the PCIe settings in the FSP. However, this did not solve the problem. Does the Atom E39xx require any additional settings for normal Non-Common Clock mode operation?
Thanks for your reply.
You can send your schematics and layout implementation to be fully verified by Intel following the procedure stated on the following website:
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The schematic check has been completed, thanks to the Intel team!
I have corrected some of the identified schematic comments in the module, but nothing has changed. All interfaces except PCIe function normally: the E39xx processor does not operate adequately on the PCIe interface in Non Common Clock mode. Setting non-standard PCIe * PortX clocks with SSC in PCIE * bits (x2 controller) (entry 12a) in the descriptor also did not correct the situation. Maybe there are some registers or strap options on the GPIO pins that are not described in the documentation and that would allow the processor to work without errors E39xx the PCIe interface in Non Common Clock mode?
Best regards, @oleg36