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Is it possible to send nine SCL clock pulses using Denverton's Smbus host interface ?


I'm designing PWB which using Atom C3508(Denverton) as an I2C master at 100 kHz in order to control some slave devices such as EEPROM, and thermal sensor, DCDC with PMbus, etc.
In case such as master reseted by WDT during I2C transaction, when I2C master start next I2C communication after reset , I2C slave might be holding the SDA line low (Slave will not complete of last communication).
Accroding to I2C speficication, I2C master can clear this condition by issuing 9 clock pulses while allowing the SDA line to float, followed by a STOP bit.
Is it possible to send extra nine SCL clock pulses by Denverton's Smbus host interface in the Linux environment?

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