We are using Intel ATOM 3826 in our design. Our schematic is done and same is also reviewed by the intel schematic review support team.
We are on the PCB layout stage and for that we need pin package delay file to import in our allegro PCB design tool from cadence.
Thank you for contacting Intel Embedded Community.
The https://cdrdv2.intel.com/v1/dl/getContent/512611 Bay Trail Trace Length Calculator (TLC) document # 512611, https://cdrdv2.intel.com/v1/dl/getContent/523692 Bay Trail-I Platform TLC Addendum document # 523692, and https://cdrdv2.intel.com/v1/dl/getContent/512379 Bay Trail-I Platform Design Guide (PDG) document # 512379 has the information that may help you.
These documents are accessible when you are logged into your Resource & Design Center (RDC) privileged account.
We hope that this information is useful to you.
Thanks for the input.
We have seen the TLC sheet (523692-523692-rev-3p0-bay-trail-i-tlc) for the Intel Atom. Looks like we need to put package delay for each pin manually.
This will be a big task for us & time consuming. In our general practice of FPGA routing we get the package delay file from the Xilinx tool and the same we used to port in our layout.
Can you provide a similar sheet with pin no vs pin delay information for the Intel Atom E3826 so that same we port in the layout?
Thanks for your updates.
In order to be on the same page, could you please show us with screenshots the cited situation?
Waiting for the information that should answer this question.