Hi Community members and Intel support team,
We are undergoing a software development on an embedded board with Intel Atom Processor E3845. Since this board supports ECC memory module, there should be registers to hold the status of memory activities, like any ECC error detected and corrected, or any uncorrectable error occurred. After reading the Atom Processor E3800 series datasheet (# 538136, Rev3.5) in below link:
We already found some registers that are useful. Examples are
1/ P.301, the DECCCTRL (DECCCTRL) – offset 60h
2/ P.302, the DECCSBECNT (DECCSBECNT) – offset 62h
However, to fully understand the registers, this document does not provide enough information. For example, we need the location of register
1/ ERRNERR (FERRNERR)— the First Error and Next Error Register.
We believe that the document # 538136 does not include all the descriptions of registers. For example, on P.301, the register between location DECCCTRL and DECCSBECNT, offset 61h is missing. We believe the missing locations are the registers we want.
In another project, we were already able to utilize these registers successfully on Atom Bay-trial-I CPU C2750 based on the document: "Intel® Atom™ Processor C2000 Product Family for Communications Infrastructure External Design Specification (EDS)", document # 510524. The required registers are starting from P.875.
So, we would like to ask if there are another document besides # 538136 which includes all the register description?
This enquiry has already post in Intel support and their engineer advise us to post it on communities, your help is greatly appreciated! Thank you for reading this long post!
Please check document # 510858: Bay Trail-I SoC External Design Specification For Bay Trail platforms based on the Bay Trail-I SoC,
section 13.1 Register Map, includes a register description. Please let us know if you need additional information about it.
We keep looking for the detailed information requested.
Document # 510858 has been delivered to you via email it has not yet been published to the EDC. Hope this helps! Please note that it is classified as Intel Confidential. Thanks!
Hi JC, LynnX,
Thank you for the reply!
I checked my mail box including the junk box but still cannot find your reply with # 510858. My mail address in my profile is correct. Would you send again please?
We are requesting the upload of the file to the EDC Library.
We will let you know as soon as file is available.
I have received your mail this morning, with document # 510858 Bay Trail-I SoC External Design Specification Revision 1.5, July 2013. After checking with your suggested 13.1 section, I still cannot see my required memory register information.
When comparing the new received # 510858 and the # 538136 Atom Processor E3800 series datasheet on hand, they looks very alike. On # 538136 there are some of the memory registers I need on section 12.3 - System Memory Controller (D-unit) Message Registers, but there is no such 12.3 section in # 510858.
To be clear I would like to get the location and decriptions of System Memory Controller (D-unit) Message Registers like this one.
FERRNERR (FERRNERR) - the First Error and Next Error register
Would you check if any of Intel documents of E3800 series Processor have description of such registers?
Unfortunately we are not able to provide that information over this thread.
If you would like to be connected with an Intel representative in your area to further discuss your project, please let us know and we will facilitate that introduction.
Sorry for the late reply, yes we would like to be connected with Intel representative. Please help on facilitating the introduction.