apollolake: FSP: PCIe stop/resume during silicon init

[CGmei]

I am using latest coreboot with latest APL FSP from Intel. On my device there is a custom PCIe device using a Lattice FPGA.

FSP does the following actions during silicon init:

• PCIe link training
• PCIe link stop
• PCIe link training

The used Lattice PCIe IP core has some problems with this sequence and from time to time the Lattice PCIe core state machine jumps into the worng state caused by the training/stop dance. Is there any FSP option to disable this behavior?

Thanks

[CarlosAM_INTEL]

Hello, @CGmei​:

Thank you for contacting Intel Embedded Community.

Could you please confirm that you are following the guidelines stated in the Apollolake Intel(R) Firmware Support Package (FSP) Integration Guide? This document can be found at:

https://usermanual.wiki/Document/ApolloLakeFSPIntegrationGuide.56175485.pdf

We are waiting for your reply.

Best regards,

@Mæcenas_INTEL​.

[CGmei]

Yes... I am following that. What needs to be done to get access to a debug version of the FSP?

[CarlosAM_INTEL]

Hello, @CGmei​:

Thanks for you update.

The FSPs available can be found as a reference at the following website:

https://github.com/IntelFsp/FSP

In the case of the Apollo Lake, the FSPs available are stated as a reference at:

https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg

The consultations related FSP issues should be addressed as a reference at the following website:

https://github.com/IntelFsp/FSP/issues

Best regards,

@Mæcenas_INTEL​.

[CGmei]

Thanks for all the links but thats nothing new - sorry. I have created an github issue as you told me but I do not have much hope.

As the company I work for have signed NDAs with Intel is there no way to acclereate this process?

We really need to understand and fix this issue.

[CarlosAM_INTEL]

Hello, @CGmei​:

Thanks for your update.

We have contacted you via email.

Best regards,

@Mæcenas_INTEL​