I am using latest coreboot with latest APL FSP from Intel. On my device there is a custom PCIe device using a Lattice FPGA.
FSP does the following actions during silicon init:
The used Lattice PCIe IP core has some problems with this sequence and from time to time the Lattice PCIe core state machine jumps into the worng state caused by the training/stop dance. Is there any FSP option to disable this behavior?
Thank you for contacting Intel Embedded Community.
Could you please confirm that you are following the guidelines stated in the Apollolake Intel(R) Firmware Support Package (FSP) Integration Guide? This document can be found at:
We are waiting for your reply.
Thanks for you update.
The FSPs available can be found as a reference at the following website:
In the case of the Apollo Lake, the FSPs available are stated as a reference at:
The consultations related FSP issues should be addressed as a reference at the following website:
Thanks for all the links but thats nothing new - sorry. I have created an github issue as you told me but I do not have much hope.
As the company I work for have signed NDAs with Intel is there no way to acclereate this process?
We really need to understand and fix this issue.