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sbass
Beginner
1,974 Views

braswell enable/disable pci device

Hello,

i try activated pci device 28 function 0 , 22C8h pcie Port 1:

i use register: Function Disable (FUNC_DIS)—Offset 34h

FUNC_DIS_BITS bit 20 - PCIE* function 0 set 0.

After write bit 20 set to 0, i read this register and this bit always 1.

Can you enable pci device by this register ?

is there another solution for activate this pci device (device 28 function 0 , 22C8h pcie Port 1) ?

Best regards,

Sébastien

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9 Replies
Adolfo_S_Intel
Moderator
209 Views

Hello keziaha

Could you please let me know how are you changing the state of the bit?

Are you using a third party program? Are you developing your own application?

What operating system are you using?

Are you using your own board or a third party board?

I will be waiting for your feedback.

Best regards,

Adolfo Sanchez

sbass
Beginner
209 Views

Hello Adolfo,

We have design our board with braswell cpu, for boot i use coreboot + fsp.

I develop in coreboot, so i write directly in register :

pmc_base + func_dis: 0xfed03000 + 0x34 set bit 20 for pcie function 0

My goal is pcie port 1 (function 0) is always enable, power on , even without device connected on line pci.

Sébastien

CarlosAM_INTEL
Moderator
209 Views

Hello, keziaha:

Thanks for your reply.

The information that may help you as a reference is stated at:

https://mail.coreboot.org/pipermail/coreboot-gerrit/2015-November/036179.html https://mail.coreboot.org/pipermail/coreboot-gerrit/2015-November/036179.html

https://github.com/coreboot/coreboot/blob/master/src/soc/intel/braswell/include/soc/pcie.h coreboot/pcie.h at master · coreboot/coreboot · GitHub

https://github.com/coreboot/coreboot/blob/master/src/soc/intel/braswell/pcie.c coreboot/pcie.c at master · coreboot/coreboot · GitHub

We hope that this information may help you.

Best regards,

Carlos_A.

sbass
Beginner
209 Views

Hello,

here my trace :

src/soc/intel/braswell/chip.c/enable_dev ( Intel Braswell SoC ), type: 2

vendor: 0xffff. device: 0xffff

class: 0xff Unassigned class

subclass: 0xff ???

prog: 0xff

revision: 0xff

src/soc/intel/braswell/southcluster.c/southcluster_enable_dev ( Intel Braswell SoC )

PCI: Static device PCI: 00:1c.0 not found, disabling it.

PCI: 00:1c.0 [ffff/ffff/00ffff] has unknown header type ff, ignoring.

PCI: 00:1c.0 [ffff/ffff] enabled No operations

pci_probe_dev dev

pci_probe_dev enable device

----------

src/soc/intel/braswell/chip.c/enable_dev ( Intel Braswell SoC ), type: 2

vendor: 0x8086. device: 0x22ca

class: 0x06 Bridge

subclass: 0x04 PCI bridge

prog: 0x00

revision: 0x35

src/soc/intel/braswell/southcluster.c/southcluster_enable_dev ( Intel Braswell SoC )

PCI: 00:1c.1 [8086/0000] bus ops

src/soc/intel/braswell/pcie.c/pcie_enable ( Intel Braswell SoC )

src/soc/intel/braswell/pcie.c/check_port_enabled ( Intel Braswell SoC )

src/soc/intel/braswell/pcie.c/check_device_present ( Intel Braswell SoC )

src/soc/intel/braswell/southcluster.c/southcluster_enable_dev ( Intel Braswell SoC )

PCI: 00:1c.1 [8086/22ca] enabled

pci_probe_dev dev

pci_probe_dev enable device

i don't see vendor id and device id of device port 1:

vendor: 0xffff. device: 0xffff

class: 0xff Unassigned class

Why ? device pcie port 1 is disable before?

On device port2 we see vendor id and device id , pcie_enable is launched after .

CarlosAM_INTEL
Moderator
209 Views

Hello, keziaha:

Thanks for your reply.

In order to provide the proper support, could you please answer the questions stated in our communication of the past May 9th, 2017 specifically at 2:03 PM?

Waiting for your reply.

Best regards,

Carlos_A.

sbass
Beginner
209 Views

Hello,

Could you please let me know how are you changing the state of the bit?

--> pmc_base + func_dis: 0xfed03000 + 0x34 set bit 20 for pcie function 0

Are you using a third party program? Are you developing your own application?

--> i use coreboot + fsp intel.

What operating system are you using?

--> no operating system.

Are you using your own board or a third party board?

--> we have our own board.

I will be waiting for your feedback.

CarlosAM_INTEL
Moderator
209 Views

Hello, keziaha:

Thanks for your update.

The information that may help you, which must be reviewed with the assistance of your BIOS vendor, is stated in sections 37.3 and 37.2, on pages 387 and 386 of the https://edc.intel.com/Link.aspx?id=10022 Braswell System-on-Chip (SoC) BIOS Writers Guide document # 541233.

We hope that this information is useful to you.

Best regards,

Carlos_A.

sbass
Beginner
209 Views

Carlos,

Ok, but, i don't have bios vendor but i use FSP INTEL for braswell with coreboot. In coreboot no code corresponding " Root Ports Function Disable Flow". For me it's FSP disable root port. But i don't have souce code . fsp take in input device tree, there is maybe an solution for not disable root port?

And in datasheet, i don't have description register :

D28:Fn + 0x420

D28:Fn + 0xF4

D28:Fn + 0x338

D28:Fn + 0xE0

D28:Fn + 0x408

....

Otherwise, Can we enable root ports after disable this root Ports ?

Sébastien

CarlosAM_INTEL
Moderator
209 Views

Hello, keziaha:

Thanks for your reply.

In order to help you, we will send an email.

Best regards,

Carlos_A.

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