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SNich2
Beginner
903 Views

crown bay bldk initial startup

I have a couple of 'getting started' type questions.

Out of the box the crown bay BLDK builds a 1 meg image, however the SPI flash is a 2 meg part. Do I program it at zero or at a 1 meg offset?

Can I assume that all address settings are correct as the package is delivered for the "little bay + shell bay == crown bay" package?

I have the alpha drop of the of the Crown bay bldk, but when I flash it the system is unrepsonsive and I can no longer connect through the XDP port (Lauterbach). I am under the assumption that the 'SPI' loader in Tunnel Creek, is not happy with what it is finding in SPI flash and is failing to move it to RAM. (Incorrect siginiture in the Micro-Code)? I can reflash the BIOS as delivered and all returns to a working state, debugger etc. Without the debugger or any documentation on the SPI loader block in Tunnel creek I am at a loss to debug what I am doing wrong. Thanks

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Qi_W_Intel
Employee
66 Views

You should program the flash staring from 1 M as the reset vector is sitting in the top of the flash.

What the Port 80's display after the BLDK image is flashed. With this information, you could check the calling of funciton ' checkpoint(0x20)' to know where the hang is in the files such as 'init.c'.

Regards

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