I am having problems with DIMM B on a Haswell processor based design.

[PWilc1]

We have a design using a Haswell processor with one DIMM on

each DDR controller. DIMM A seems to work. When using DIMM B

the system fails to boot and sometimes fails in the BIOS. We believe

we have followed the recommendations in 490765_Intel_2013_Platform_SM-ATLC_Rev0p70.xlsm

and the Intel document 486711/486712. These were downloaded in 9-Mar-2016 and

29-Jan-2015 respectively. Have either of these documents been updated or have their

contents been superceded by a Specification Update or other document?

Thanks, Paul.

[CarlosAM_INTEL]

Hello, PVWB:

Thank you for contacting the Intel Embedded Community.

In order to better understand this situation, we would like to address the following questions:

Could you please let us know the part numbers of the processor and chipset related to this situation?

Could you give us all the information of the Memories that you are using?

Could you clarify if this situation happens with your design or with a Customer Reference Board (CRB)? How many units are affected? How often it happens? In case that this issue is related to your design, could you please reproduce this issue in a CRB, and lets us know the consequences?

Could you please update the BIOS to the latest version, replicate the listed circumstance, and let us know the effects of this change? By the way, please give us all the information of the BIOS.

Please give us all the information requested through the previous questions to better understand this problem.

Best regards,

Carlos_A.

[PWilc1]

Dear Carlos,

We use E3-1268Lv3 with DH82C226 PCH companion part.

We have tried Apacer 78.A1GDF.AFG0C and Ballistics

BLS4G3D1609ES2LX0.16FER2 DIMMs. These same DIMMs

work fine in the A DIMM slot, not in the B slot.

We think this is probably a layout problem. We wanted to be

absolutely sure that we have current documentation for

trace lengths and trace matching and trace lengths within the

processor package, before we do another PCB revision.

Thanks, Paul.

[CarlosAM_INTEL]

Hello, PVWB:

Thanks for your update.

It is important to let you know that you are implementing a Denlow platform.

Due to this fact, we suggest you follow the guidelines stated in section 4 of the https://www-ssl.intel.com/content/www/us/en/secure/intelligent-systems/privileged/core-q87-chipset-is-guide.html Haswell Desktop and Denlow-WS Platform Design Guide (PDG) For Use with Haswell Processor and Haswell Platform Controller Hub (PCH) document # 486711.

We hope that this information may help you.

Best regards,

Carlos_A.

[PWilc1]

Dear Carlos,

Thank you for your help so far.

The version of the 486711 document I have is Rev 2.3 dated Sep 2014.

Is this the latest version of this? Also, this document doesn't contain

the lengths of signals within the Haswell package. These are only available

in the 490765_Intel_2013_Platform_SM-ATLC_Rev0p70.xlsm spreadsheet

as far as I know. Are the numbers in this spreadsheet correct, or do more

recent versions of these numbers exist?

Thanks, Paul.

[CarlosAM_INTEL]

Hello, PVWB:

Thanks for your reply.

The document # 486711 that we have mentioned is the version 2.4 of October 2015.

On the other hand, the document # 490765 has been changed to document # 566424 that is revision 1.0 of March 2016.

We hope that this information may help you.

Best regards,

Carlos_A.