Intel Physical Layer EV Tool - SATA Margining - Loopback mode "functional" not offered

[UGuth1]

Hi all,

I am trying to do SATA margining tests on a Skylake system using Intel Physical Layer EV Tool Version 1.13.1.

The manual (document 562291, Revision 1.12.7) states that for this test the user should select loopback mode "Functional" - but this is exactly the item that is not offered in the list.

Any ideas?

Many thanks in advance!

Best regards,

Uwe

[CarlosAM_INTEL]

Hello, Uwe_Guth :

Thank you for contacting Intel Embedded Community.

In order to be on the same page, could you please tell us if the affected project has been designed by you or a third-party company? If it is a third-party design, could you please give me all the information related to it? In case that it has been designed by you, could you please confirm us if it has been reviewed by Intel?

Please give us the information that may answer the previous questions.

We really appreciate your collaboration.

Best regards,

Carlos_A .

[UGuth1]

Hello Carlos,

thank you very much for your quick response.

The affected project has been designed by us. It has not been reviewed by intel. It is a COM Express design which basically works flawlessly, but a customer of ours wants to see results of the margining tests of a system consisting of our CPU module and his carrier board.

Best regards,

Uwe

[CarlosAM_INTEL]

Hello, Uwe_Guth :

Thanks for your reply.

Based on your previous communications, could you please give us the part numbers and SKUs of the processors and chipsets related to this situation?

Could you please tell us the way to obtain the "Intel Physical Layer EV Tool Version 1.13.1"?

Could you please let us know if this situation happens with the https://cdrd.intel.com/v1/dl/getContent/562291 Intel Physical Layer Electrical Validation Tool Ver 1.12.7 document # 562291?

Please let us know all the information that should answer the previous questions.

Best regards,

Carlos_A.

[UGuth1]

Hello Carlos,

The PLEVT Revision 1.13.1 is part of the package you sent me the link of ( https://cdrd.intel.com/v1/dl/getContent/562291 Intel Physical Layer Electrical Validation Tool Ver 1.12.7)

Hmmm ..... probably I should mention, that I just used the file IntelPLEVT.efi on a USB Stick?

I tried both Versions 1.12.4. and 1.13.1 of this file, same result.

SKU's are:- GLCM236, S-Spec SR2CE- CPU is a core i3-6100E, S-Spec SR2DV

Best regards,

Uwe

[CarlosAM_INTEL]

Hello, Uwe_Guth :

Thanks for your clarification.

The cited tool is compatible with https://ark.intel.com/products/codename/55887/Lewisburg# @embedded Lewisburg (LBG) chipset and https://ark.intel.com/products/codename/63508/Denverton?q=denverton# @embedded Denverton (DNV) SoC, which are totally different than the ones that you are using.

You can confirm this information in section 1, on page 1 of the https://cdrd.intel.com/v1/dl/getContent/562291 Intel(R) Physical Layer Electrical Validation Tool [Intel(R) PLEVT] User Guide document # 562291.

We hope that this information may help you.

Best regards,

Carlos_A .

[UGuth1]

Hello Carlos,

thank you very much for your information.

Well, the tool seems to support it according to the attached picture. BUT probably just for the compliance tests.

If so, could you help me out with a tool that supports Skylake? Probably also the PEG Port?

Thank you very much in advance!

Kind regards,

Uwe

[CarlosAM_INTEL · Accepted solution]

Hello, Uwe_Guth :

Thanks for your update.

The https://cdrd.intel.com/v1/dl/getContent/557800 Intel Electrical Margin Tool (EMT) for Skylake Platform document # 557800 is the one that may help you because it tests PEG and SATA interfaces.

We hope that this information is useful to you.

Best regards,

Carlos_A.

[UGuth1]

Hello Carlos,

thank you very much for your help - that's exactly what I have been looking for.

I just wonder, why I am unable to find this tool on your homepage; even when looking for the document number?

Anyhow - it works nicely, and I have been able to get some nice results.

Best regards,

Uwe

[CarlosAM_INTEL]

Hello, Uwe_Guth :

Thanks for your reply.

The listed document is classified as Intel confidential, which requires a CDNA between your company and Intel as well as a Privileged Resource & Design Center (RDC) account. It can be requested by filling out the form stated at the following website:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html https://www.intel.com/content/www/us/en/forms/design/contact-support.html

We are glad that the provided information is useful to you.

Best regards,

Carlos_A.

[UGuth1]

Hello Carlos,

thank you very much.

Best regards,

Uwe