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PCI Express 'No Snoop Enable' and cacheable/non-cacheable regions

CGard3
Beginner
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Hi,

what would happen if a PCI Express packet is sent to memory with the "No Snoop" attribute set in the header but the target memory region is cacheable and indeed cached in at least one core.

Is this calling for disaster or is "No Snoop" just a fast write back path without actually disabling cache coherency checks? (e.g. invalidate occurs parallel to memory write)

Thanks,

Charles

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