Tiger Lake UP3 for IOTG design

[SXL]

Hi Intel guys, I'm tring to power on a board with TGL UP3 processor(S-SPEC=SRK08), this board design is based on intel reference design(RDC#: 626256), during power on process, we encounter some problems, could you kindly help to give me a favor ?

The problems list as below:

1. some board can not generate 38.4M clock, I want to know the condition to generate this clock;

2. when CPU recieve the input signal VCCST_PWRGD, what does the CPU do with PMIC

[CarlosAM_INTEL]

Hello, @SXL:

Thank you for contacting Intel Embedded Community.

Could you please let us know if the affected design has been verified by Intel?

We are waiting for your clarification.

Best regards,

@CarlosAM_INTEL.

[SXL]

Hi CarlosAM,

   Actually, I don't know whether the reference design (RDC#: 626256) is verified by intel or not, could you help to confirm?

[CarlosAM_INTEL]

Hello, @SXL:

Thanks for your reply.

You should follow the steps stated in the following website to fully verify the schematics and layout of your design:

https://edc.intel.com/Tools/Design-Review/Default.aspx

Best regards,

@CarlosAM_INTEL.