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akong
Beginner
1,267 Views

max10 on chip flash write issue (without nios)

max10 on chip flash write issue (without nios)

hi, can anyone help to answer this question?

I am trying to write data to max10 on chip flash(UFM) without using NIOS.

what i am doing is to write a simple controller module and send the control signal required by on_chip_flash ip.

The steps can be described as follows:

1, disable write protection

2, do sector erase

3, write data to UFM

4, read back the data and verify the writing is successful or not.

5, enable write protection bit

my question is if i read back signal after write, data is correct. However, if i disable the write process, and read the address

directly (same address as i write before), the data is always FFFF. It seems that the data is not write into flash successfully.

However, during the wite process, the statue signal from avmm_csr_readdata shows that the erase/write operation is successful.

And the data can be read back correctly after the write process. Please help to solve this problem. Thanks!

Attached please find the cource code of the controller.

module main_controller

(

clock,

reset_n,

UFM_ADDRESS1,

UFM_ADDRESS2,

display_count1,

display_count2,

data_valid,

csr_status,

CSR_IDLE,

CSR_OP_WRITE_PASS,

CSR_OP_READ_PASS,

CSR_OP_ERASE_PASS,

CSR_BUSY_ERASE,

CSR_BUSY_WRITE,

CSR_BUSY_READ,

write_protect,

mc_state_machine

);

parameter COUNTER_BITS = 32;

parameter read_only = 1;

input clock;

input reset_n;

input [19:0] UFM_ADDRESS1;

input [19:0] UFM_ADDRESS2;

input [COUNTER_BITS-1:0] display_count1; //

input [COUNTER_BITS-1:0] display_count2;

output reg data_valid; //

output [9:0] csr_status;

output CSR_IDLE;

output CSR_OP_WRITE_PASS;

output CSR_OP_READ_PASS;

output CSR_OP_ERASE_PASS;

output CSR_BUSY_ERASE;

output CSR_BUSY_WRITE;

output CSR_BUSY_READ;

output [4:0] write_protect;

output [5:0] mc_state_machine; //

///////////////////////////////////////////////

// mc_state_machine states

`define IDLE 6'b000000

`define FETCH_FLASH 6'b000001

`define FLASH_READ1 6'b000010

`define FLASH_READ2 6'b000011

`define FLASH_READ3 6'b000100

`define FLASH_READ4 6'b000101

`define READ_FLASH_DONE 6'b000110

`define WAIT_FOR_INIT_SHUTDOWN 6'b000111

`define START_SHUTDOWN 6'b001000

`define CSR_MASK_OFF1 6'b001001

`define CSR_MASK_OFF2 6'b001010

`define CSR_MASK_OFF3 6'b001011

`define CSR_MASK_OFF4 6'b001100

`define CSR_READ1 6'b001101

`define CSR_READ2 6'b001110

`define CSR_READ3 6'b001111

`define CSR_READ4 6'b010000

`define CSR_READ5 6'b010001

`define CSR_READ6 6'b010010

`define FLASH_WRITE0 6'b010011

`define FLASH_WRITE1 6'b010100

`define FLASH_WRITE2 6'b010101

`define FLASH_WRITE3 6'b010110

`define FLASH_WRITE4 6'b010111

`define FLASH_WRITE5 6'b011000

`define FLASH_WRITE6 6'b011001

`define FLASH_WRITE7 6'b011010

`define FLASH_WRITE_DONE 6'b011011

`define FLASH_VERIFY1 6'b011100

`define FLASH_VERIFY2 6'b011101

`define FLASH_VERIFY3 6'b011110

`define FLASH_VERIFY4 6'b011111

`define CSR_MASK_ON1 6'b100000

`define CSR_MASK_ON2 6'b100001

`define CSR_MASK_ON3 6'b100010

`define CSR_MASK_VERIFY1 6'b100011

`define CSR_MASK_VERIFY2 6'b100100

`define CSR_MASK_VERIFY3 6'b100101

`define POWER_DOWN_READY 6'b100110

////////////////////////////////////////////////

reg [19:0] avmm_data_addr;

reg avmm_data_read;

reg [31:0] avmm_data_writedata;

reg avmm_data_write;

reg [3:0] avmm_data_burstcount;

wire [31:0] avmm_data_readdata;

reg avmm_csr_addr;

reg avmm_csr_read;

reg [31:0] avmm_csr_writedata;

reg avmm_csr_write;

reg [31:0] flash_dataout1, flash_dataout2;

reg [5:0] mc_state_machine;

wire [31:0] avmm_csr_readdata;

wire avmm_data_waitrequest;

wire avmm_data_readdatavalid;

assign csr_status = avmm_csr_readdata[9:0];

assign write_protect= avmm_csr_readdata[9:5];

////////////////////////

//wire CSR_IDLE, CSR_OP_WRITE_PASS,CSR_OP_READ_PASS,CSR_OP_ERASE_PASS;

assign CSR_IDLE=(csr_status[1:0]==2'b00)?1'b1:1'b0;

assign CSR_BUSY_ERASE=(csr_status[1:0]==2'b01)?1'b1:1'b0;///5'bxxx01

assign CSR_BUSY_WRITE=(csr_status[1:0]==2'b10)?1'b1:1'b0;///5'bxxx10

assign CSR_BUSY_READ=(csr_status[1:0]==2'b11)?1'b1:1'b0;///5'bxxx11

assign CSR_OP_WRITE_PASS=(csr_status[3]);<...

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6 Replies
CarlosAM_INTEL
Moderator
143 Views

Hello, spacetimerake:

Thank for contacting Intel Embedded Community.

In order to be on the same page, could you please tell us the part number and SKU of the device related to this thread? Please give us all the information related to them.

Wating for your reply.

Best regards,

Carlos_A.

akong
Beginner
143 Views

Hi Carlos A,

thanks for your prompt reply. my controller code is test using MAX10 FPGA Evaluation Kit https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-ma... MAX 10 FPGA Evaluation Kit

P/N=EK-10M08E144ES/P

regards

CarlosAM_INTEL
Moderator
143 Views

Hello, spacetimerake:

Thanks for your clarification.

The hardware consultations related to this device or any FPGA product family device should be addressed to the following website:

https://forums.intel.com/s/topic/0TO0P000000MWKDWA4/fpga-soc-and-cpld-boards-and-kits?language=en_US https://forums.intel.com/s/topic/0TO0P000000MWKDWA4/fpga-soc-and-cpld-boards-and-kits?language=en_US

We hope that this information may help you.

Best regards,

Carlos_A.

akong
Beginner
143 Views

Thanks for the reply. But I can not find useful information which can help to solve this problem. Can someone help to answer this question?

regards

CarlosAM_INTEL
Moderator
143 Views

Hello, spacetimerake:

Thanks for your reply.

Please let me paraphrase my previous message.

The proper persons to help you with your consultations can be found at the cited forum, please address your consultations through this channel.

Best regards,

Carlos_A.

akong
Beginner
143 Views

many thanks for the help. I have post my question to the correct forum.

regards

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