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Intel Compiler VS GCC for mov operation

NStoj
Beginner
690 Views

Hello,

 

We have an issue with Intel Compiler when compiling this set of code:

 

asm volatile(

"mov %%cr4,%%rax\n\t"

"orq $0x406F0,%%rax\n\t"

"mov %%rax,%%cr4\n\t"

 

"mov %%cr0,%%rax\n\t"

"orq $0x2,%%rax\n\t"

"orq $0x10,%%rax\n\t"

"orq $0x20,%%rax\n\t"

"mov %%rax,%%cr0\n\t"

: : : "rax");

 

For all mov related operation it will add rex.W prefix.   

627a: 48 0f 22 c0     rex.W mov %rax,%cr0

 

GCC will not do that:

7137: 0f 22 c0       mov  %rax,%cr0

 

In our system we are using bare-metal application to run on CPU Core and when executing rex.W mov %rax,%cr0 it will generate a fault in our case.

 

Can somebody explain what Intel Compiler is doing there, why Intel compiler is deviating from Intel's instruction manual?

 

0 Kudos
5 Replies
Adolfo_S_Intel
Moderator
264 Views

Hello @NStoj​  I am consulting this case and will provide more information as soon as possible.

 

Adolfo_S_Intel
Moderator
264 Views

Hello @NStoj​  Are you using some sample code, or creating your own code? Are you using any flags on the compiler?

 

Best Regards,

Adolfo Sanchez

NStoj
Beginner
264 Views

Hello @AdolfoS_Intel​ 

 

Thank you for the reply.

 

Code is used to enable SSE and AVX instruction set and we made trough Intel® 64 and IA-32 Architectures Software Developer’s Manual.

Flags which are passed to Intel compiler are:

-m64 -nostdinc -isystem -Ofast -march=broadwell -funroll-loops -Wall -Wstrict-prototypes -Wtype-limits -Wmissing-declarations -Wmissing-prototypes \

-fno-strict-aliasing -fomit-frame-pointer -fno-pic -fno-common -fno-stack-protector -ffreestanding -ffunction-sections \

-mno-red-zone

 

Best regards,

Nikola

NStoj
Beginner
264 Views

Hello @AdolfoS_Intel​,

 

Any news ?

 

Best regards,

Nikola

 

CarlosAM_INTEL
Moderator
264 Views

Hello, @NStoj​ :

 

Thanks for your reply.

 

We suggest you address this thread to the forum stated at the following website:

 

https://software.intel.com/en-us/Forum

 

Best regards,

@Mæcenas_INTEL​.

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