I have a design based off YubaCity eval and CPLD, but during power-up, the board re-enters DeepSx mode by asserting SLP_SUS_N.
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Could you please give the part number of the processors associated with this request? Could you please tell us if the projects related to this forum have been designed by you or by a third-party company? In case that they are third-party units please give the part number, model, name of the manufacturer, where it is stated the information related to it. In case it is your design, could you please clarify it has been reviewed by Intel and list the sources that you have used to develop it?
We are waiting for your answer to these questions.
The part number is D-2146NT (FH8067303782601S R3ZR)
I am the designer of the project. We started with YubaCity eval schematic and modified for our application.
I am using the YubaCity verilog module version 0.9, but it was written for the Infineon power solution.
Infineon would not engage with us due to volume, so we went with the Intel approved alternate from Texas Instruments.
Does Intel have a CPLD revision for that or would they know the changes to make? The issue I am having is the power cycle
starts and a second later, the CPU goes back to DeepSx mode.