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Hi Support Team,
For custom board we are using Broadwell-DE Xeon processor D1559 and 9 on board x8 Dram devices.
We are performed simulation in Hyperlynx DDR4 Batch simulation and observing the following errors.
- In write Overshoot area Margin is Failing.
- For Clock Signal Vix is failing.
Kindly provide your Inputs/suggestions
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Hello, @KMANO3:
Thank you for contacting Intel Embedded Community.
In order to help you, we want to address the following question:
Could you please confirm if this thread is related to the following?
https://forums.intel.com/s/question/0D50P00004VGKGpSAP/ddr4-controller-timing-parameters-in-xeon-d15...
Could you please confirm that you have received our communication via email of the past Thursday February 13th, 2020?
We are waiting for your confirmation.
Best regards,

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