Performed DDR4 Timing Analysis Broadwell -DE Xeon Processor D1559 DDR4 Timing Parameters

[KMANO3]

Hi Support Team,

For custom board we are using Broadwell-DE Xeon processor D1559 and 9 on board x8 Dram devices.

We are performed simulation in Hyperlynx DDR4 Batch simulation and observing the following errors.

1. In write Overshoot area Margin is Failing.
2. For Clock Signal Vix is failing.

Kindly provide your Inputs/suggestions

[CarlosAM_INTEL]

Hello, @KMANO3​:

Thank you for contacting Intel Embedded Community.

In order to help you, we want to address the following question:

Could you please confirm if this thread is related to the following?

https://forums.intel.com/s/question/0D50P00004VGKGpSAP/ddr4-controller-timing-parameters-in-xeon-d15...

Could you please confirm that you have received our communication via email of the past Thursday February 13th, 2020?

We are waiting for your confirmation.

Best regards, 

@Mæcenas_INTEL​.