Hi Support Team,
For custom board we are using Broadwell-DE Xeon processor D1559 and 9 on board x8 Dram devices.
We are performed simulation in Hyperlynx DDR4 Batch simulation and observing the following errors.
- In write Overshoot area Margin is Failing.
- For Clock Signal Vix is failing.
Kindly provide your Inputs/suggestions
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