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We are redesigning the board with on board X8 DDR4 devices, while cross checking the reference design we saw that the TDQS line of the DDR4 chips are connected to the DQS 9-17 of the xeon.

KMANO3
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Are those TDQS connection mandatory? Also we are not using the registers for the address and command lines, is this okay?

Also we would like to know whether the SOC DDR clock can drive 9 chips as we are using single rank configuration.

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