Data over ethernet - with a NIOS maybe? Help needed for the QSYS system

[Altera_Forum]

Hello everyone, 

I have developed an IP which uses the Avalon ST protocol for receiving and transmitting data. I want to now create a BSP to test the functionality on FPGA. I took the simple socket server example and I was able to run it as is. I now want to tweak it and add my IP as a part of the QSYS system.  What I noticed is that the data from the TSE MAC is sent to a Scatter-Gather DMA, which is then written to a Descriptor memory (RX chain). The NIOS has access to this memory. Similarly, for the TX chain, the NIOS writes to this descriptor memory -> Scatter Gather DMA (MM to streaming) -> TSE MAC TX.  Now I would like to connect the incoming frames data to the input of my block, i.e. RX for TSE MAC -> My IP. One thing is that the TSE MAC just removes the first few bytes of the header, so I would have to create another IP to strip the rest of the header and pass only the payload to my IP. If I decide to do this, the sample example chain of TSE MAC -> SGDMA -> descriptor memory ->NIOS will no longer be valid ( as I can connect the RX stream to only one sink). If this chain does not exist, the negotiation for the IP address configuration on NIOS (sample design) will not work.  The other option would be to let the data go to NIOS, send the data to another Scatter Gather DMA, convert it to a data stream, and send it to my IP block. This way the data always has to go through the NIOS. I can also use NIOS to strip the rest of the ethernet header and send just the payload to my IP block.   What would you suggest would be a better option? I have attached a picture of a proposed system following the second option. The data from ST_adapter_0 will be connected to my IP.  One other question. Is it possible to send the same data on two different channels? (Using the channel property of the Avalon streaming interface). In this case, both the NIOS and my IP can listen to the same incoming data.  Thank you, Divya

[Altera_Forum]

Dear, 

I don't have the correct answer but, I would suggest you for this. I have done the similar project a few months back. If you use bidir or iobuffer you can get what you wanted.

[Altera_Forum]

--- Quote Start ---  Dear, I don't have the correct answer but, I would suggest you for this. I have done the similar project a few months back. If you use bidir or iobuffer you can get what you wanted.  --- Quote End ---    Could you elaborate a little more? Do you mean to create bidirectional or an iobuffer component in QSYS? If so, how would that be connected?   Thank you.

[Altera_Forum]

Hi Divya, 

 Usually only the descriptors for the SGDMA are stored in Descriptor Memory. The rx data is normally written in the RAM. Look where the m_write port of your rx SGDMA is connected.  If your application is not time critical you may add an other SGDMA controller to your QSYS which copies the data after being received to your IP.  Jens

[Altera_Forum]

--- Quote Start ---  Hi Divya,  Usually only the descriptors for the SGDMA are stored in Descriptor Memory. The rx data is normally written in the RAM. Look where the m_write port of your rx SGDMA is connected.  If your application is not time critical you may add an other SGDMA controller to your QSYS which copies the data after being received to your IP.  Jens  --- Quote End ---    Thank you for this suggestion. I was under the impression that one SGDMA controller had to be connected to one block of RAM only (which is of course very limiting). I'll make a system where I have two memory spaces and I can then keep the NIOS datapath and my IP path separate. I will try this and give an update soon.