E810-XXVDA4T timeReceiver PTP period configuration

[Quantum-Aisle-LLC]

I am using Revision 1.6 646265-006 Intel® Ethernet Network Adapter E810-XXVDA4T
User Guide.

I am attempting configuration in paragraph 6.2.2 "TimeReceiver Adapter" step 3:

Set periodic output on SDP20 and SDP22 (To synchronize the DPLL1 to the E810 PHC synced by
ptp4l):

# echo 1 0 0 0 100 > /sys/class/net/$ETH/device/ptp/ptp*/period
# echo 2 0 0 1 0 > /sys/class/net/$ETH/device/ptp/ptp*/period

The first line causes "echo: write error: Input/output error." 

The second line works as expected.

What am I doing wrong?

In paragraph 4.12 "1PPS Signals from E810 Device to DPLL:"

1. To enable the frequency reference pin 10 MHz (CVL-SDP20):

# echo 1 0 0 0 100 > /sys/class/net/$ETH/device/ptp/ptp*/period
(# echo "in pin 1 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg )

The command in parenthesis does work or at least show up in pin_cfg. However, the pin state remains "invalid."

# cat /sys/class/net/$ETH/device/pin_cfg
in
| pin| enabled| state| freq| phase_delay| eSync/Ref-sync| DPLL0 prio| DPLL1 prio|
| 0| 1| valid| 1| 0| 0| 8| 8|
| 1| 1| invalid| 10000000| 0| 2| 255| 3|
| 2| 1| invalid| 1953125| 0| 0| 4| 4|
| 3| 1| invalid| 1953125| 0| 0| 5| 5|
| 4| 1| invalid| 1| 7000| 0| 1| 1|
| 5| 1| invalid| 1| 7000| 0| 2| 2|
| 6| 1| invalid| 1| 0| 0| 0| 0|
out
| pin| enabled| dpll| freq| esync|
| 0| 1| 1| 1| 0|
| 1| 1| 1| 1| 0|
| 2| 1| 0| 156250000| 0|
| 3| 1| 0| 156250000| 0|
| 4| 1| 1| 1| 0|
| 5| 1| 1| 1| 0|

I also tried the following setting:

Set Ref-Sync_pair on pin 0 & 1 (SDPs)

# echo "in pin 1 e_ref_sync 2" > /sys/class/net/$ETH/device/pin_cfg

Is this needed?

[Akshaya1]

Hi Quantum-Aisle-LLC,

Thank you for contacting Intel!

In order to assist you further, could you kindly provide the system information? This will help us address your inquiry more efficiently.

I look forward to your response.

Regards,

Akshaya 

Intel Customer Support Technician

[Akshaya1]

Hi Quantum-Aisle-LLC,

Greetings from Intel! 

This is a reminder mail regarding the issue you reported to us. 

We're eager to ensure a swift resolution and would appreciate any updates or additional information you can provide. 

 Regards,

Akshaya

Intel Customer Support Technician

[Quantum-Aisle-LLC]

Here is system information:

# uname -a
Linux Bob 6.8.0-52-generic #53~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Wed Jan 15 19:18:46 UTC 2 x86_64 x86_64 x86_64 GNU/Linux

# ethtool -i $ETH
driver: ice
version: 1.16.3
firmware-version: 4.70 0x8001f7b3 1.3755.0
expansion-rom-version:
bus-info: 0000:01:00.0
supports-statistics: yes
supports-test: yes
supports-eeprom-access: yes
supports-register-dump: yes
supports-priv-flags: yes

What is relevant is that I am using driver version 1.16.3 since my issue is 100% related to driver software.

I can set the period if I set both SMA1 and SMA2 as outputs. This seems to affect the SDP20 and SDP22 period output settings.

# echo 2 1 > /sys/class/net/$ETH/device/ptp/ptp*/pins/SMA1

# echo 2 2 > /sys/class/net/$ETH/device/ptp/ptp*/pins/SMA2

# echo 1 0 0 0 100 > /sys/class/net/$ETH/device/ptp/ptp*/period
# echo 2 0 0 1 0 > /sys/class/net/$ETH/device/ptp/ptp*/period

In the source code, I do see EIO (input/output error) can occur if pin does not support the function.

I also used the following setting for SDP20:

# echo "in pin 1 e_ref_sync 2 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg

Can I get updated documentation on the driver? As written, the version 1.6 does not work for 6.0 initial setup.

[Subhashish]

Hello Quantum-Aisle-LLC,

Greetings !!

Regarding the ongoing issue, would like to know if you have tried to reset the pins SDP20 and SDP22 before setting the output?

Regards,

Subhashish_Intel.

[Quantum-Aisle-LLC]

I played with enable and disable but this did not impact the EIO issue.

I confirmed that if I set:

# echo 2 1 > /sys/class/net/$ETH/device/ptp/ptp*/pins/SMA1

I can modify SDP20 period without getting EIO:

# echo 1 0 0 0  0> /sys/class/net/$ETH/device/ptp/ptp*/period

# echo 1 0 0 0 100 > /sys/class/net/$ETH/device/ptp/ptp*/period

Similarly, if I set

# echo 2 2 > /sys/class/net/$ETH/device/ptp/ptp*/pins/SMA2

I can modify SDP22 without getting EIO:

# echo 2 0 0 0 0 > /sys/class/net/$ETH/device/ptp/ptp*/period

# echo 2 0 0 1 0 > /sys/class/net/$ETH/device/ptp/ptp*/period

The SDP20/22 period setting does not work (returns EIO) if SMA1/SMA2 disabled

[vish1]

Hello Quantum-Aisle-LLC,

Greetings!!

Please allow us some time to review, and we will get back to you soon.

Best Regards,

Vishal Shet P

Intel Customer Support Technician

[IntelSupport]

Hi Quantum-Aisle-LLC,

Greetings for the day!

Thank you for sharing the information.

There is a change in the behavior, and we will be documenting it in the newest user guide planned to release soon.

The Steps followed in your post are accurate but right now user cannot set SDP pins. This option will be available in the new ice driver release which will be available in about 2 weeks. 

In the new functionality, user is capable of assigning channel number for a specific SDP himself now, after user does it, use the same channel number in the echo command to period file for specific pin, and afterwards a good practice is to set the same setting using pin_cfg command:

1. echo <function (0 - disabled, 1 - rx, 2 - tx)> <channel number> > /sys/class/ptp/ptp*/pins/SDP20

  echo <function (0 - disabled, 1 - rx, 2 - tx)> <channel number> > /sys/class/ptp/ptp2/pins/SDP22

2. echo <channel> <start time in s(works like a delay)> <start time in ns(works like a delay)> <frequency in s> <frequency in ns> > period file

3. echo "in pin (0 or 1 for SDPs) freq 100 (in Hz)" > /sys/class/net/$ETH/device/pin_cfg

for example:

set SDP20 to frequency 10 Mhz

echo 2 1 > /sys/class/ptp/ptp*/pins/SDP20

echo 1 0 0 0 100 > /sys/class/net/$ETH/device/ptp/ptp*/period 

echo "in pin 1 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg

set SDP22 to frequency 1 Hz

echo 2 2 > /sys/class/ptp/ptp*/pins/SDP22

echo 2 0 0 1 0 > /sys/class/net/$ETH/device/ptp/ptp*/period 

echo "in pin 0 freq 1" > /sys/class/net/$ETH/device/pin_cfg

e_ref_sync is not required to be enabled to "2" for sync to work, but it is a default option.

Regards

Jerome

Intel Customer Support Technician

[Akshaya1]

Hi Quantum-Aisle-LLC,

Greetings from Intel! 

This is a reminder mail regarding the issue you reported to us. 

We're eager to ensure a swift resolution and would appreciate any updates or additional information you can provide. 

 Regards,

Akshaya

Intel Customer Support Technician

[Quantum-Aisle-LLC]

Akshaya,

My configuration that I described above is working today. Jerome mentioned "The Steps followed in your post are accurate"

Jerome mentioned "e_ref_sync is not required to be enabled to "2" for sync to work, but it is a default option." I did not confirm that system works without this.

Jerome mentioned new ICE driver in 2 weeks on 3/28/25.

QUESTION?: Is it possible to output both 1 PPS and synchronized 10 MHz by using both SMA outputs. The documentation indicates only 10 MHz with esync (embedded 1 PPS) is possible.

Regards,

Rich

Quantum Aisle LLC

[vish1]

Hello Quantum-Aisle-LLC,

Greetings!!

Please allow us some time to review, and we will get back to you soon.

Best Regards,

Vishal Shet P

Intel Customer Support Technician

[ManoranjanDas]

Hi Richard,

Greetings for the day!

Apologies for delay in response.

Regarding your query, you can output a 10 MHz signal without needing to enable eSync. Additionally, either a 1 PPS or a 10 MHz signal can be output from any SMA connector, depending on your configuration.

Set freq to 10 MHz on output pin 1: SMA2 will drive 10 MHz signal 

# echo "out pin 1 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg

Thank you for your understanding.

Best regards,

Manoranjan

Intel Customer Support Technician

[Quantum-Aisle-LLC]

Manoranjan,

Thanks for the fast reply.

I needed to do the following to make things work:

Set freq to 10 MHz on output pin 0: SMA1 will drive 10 MHz signal 

# echo "out pin 0 freq 10000000" > /sys/class/net/$ETH/device/pin_cfg

In the discussion above and in the documented 6.2.2 "TimeReceiver Adapter," channel 1 was SDP20 10 MHz. Since SMA1 is also channel 1, I set SMA1 to 10 MHz and left SMA2 at 1 Hz. This works and the reverse with SMA2 10 MHz and SMA1 1 PPS did not.

I needed to be consistent on channel speeds. Does this make sense to you?

Regards,

Rich

[vish1]

Hello Quantum-Aisle-LLC,

Greetings!!

Please allow us some time to review, and we will get back to you soon.

Best Regards,

Vishal Shet P

Intel Customer Support Technician

[Amina_Sadiya]

Hello Team,

Thank you for your patience, Regarding your query I would like to inform you that frequency speeds should be the same on both sides.

Please let us know if you have any further questions.

Best regards,

Amina

Intel Customer Support Technician

[Akshaya1 · Accepted solution]

Hi Quantum-Aisle-LLC,

Greetings from Intel! 

This is a reminder mail regarding the issue you reported to us. 

We're eager to ensure a swift resolution and would appreciate any updates or additional information you can provide. 

 Regards,

Akshaya

Intel Customer Support Technician

[Quantum-Aisle-LLC]

Thanks,

Everything is working for me with the configurations I described above with ICE 1.6.3.

[vish1]

Hi Quantum-Aisle-LLC,

Greetings!!

Glad to hear that everything is working well with the configurations you described using ICE 1.6.3! If you need any further assistance or have additional questions, feel free to reach out. We are happy to help.

Best Regards,

Vishal Shet P

Intel Customer Support Technician