Is there a clock recovery Mechanism in TSE MAC?

[Altera_Forum]

Hi all, 

 We are using a cyclone IV fpga with a Marvell PHY through an SGMII interface. As per the Marvell datasheet  https://www.alteraforum.com/forum/attachment.php?attachmentid=7520   the interface for SGMII should be as explained in this diagram for MACs with out clock recovery.  So is there a clock recovery system inside Altera TSE MAC???  But nowhere in the ALTERA TSE MAC datasheet it is explained, how PHY should be connected in SGMII interface.  But with respect to the cyclone IV starter kit the interface is SGMII and we find, it is not as per the diagram shown above.   So please tell us is there a clock recovery option? We are not able to find any clause about the clock recovery in the TSE MAC datasheet.  Thanks and Regards, Iyan

[Altera_Forum]

Just to clarify, 

Our design is as per cyclione IV starter kit. In that, the PHY has a 25 MHz clock input. The MAC has a 125 MHz external reference clock. There is NO COMMON clock between the FPGA and the PHY.    So please tell us is there a clock recovery option in TSE MAC? We are not able to find any clause about the clock recovery in the TSE MAC datasheet.  Regards,  Santhosh

[Altera_Forum]

The GXB gigabit transceivers utilized for the SGMII interface are providing clock recovery.