What information about a p4 program using Tofino Native Architecture can be shown in a public paper? Can the the stage usage and the SRAM/TCAM usage be disclosed? If not, what metric can be used to describe the program? (I've read several public papers but still have no idea about this.)
The SDE and documents are either under Barefoot Network NDA or Intel NDA, but I cannot find any usable contact of them. The contact of Barefoot Network is no longer available. The Intel support page doesn't include the option "programmable switch". And the web page of premiersupport is always stuck in endless automatic jumps. I've searched for the contact from Intel website to Google/Bing, but cannot find any. Could anyone please give me some advice?
Sorry for my poor English.
