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SGMII interface - MDIO 0 and MDIO 1 space access??

Altera_Forum
Honored Contributor II
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Hi all, 

 

We are using a Marvell Phy IC with the altera TSE MAC IP in SGMII interface. According to the datasheet, we feel the MDIO 0 and MDIO 1 space access is as shown in the block diagram 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=7519  

 

So according to the block diagram the memory space for PCS registers are from 0x80 and for accessing PHY we have to write to the 0xA0 space. We are able to configure the PCS registers inside our MAC. But we have a feeling this configuration will not affect anything of the PHY. We are configuring only the PCS registers and we find our PHY working.  

 

But i think the PCS register dont reflect the actual status of the PHY?? Am i right in this place... 

 

So we tried accessing the PHY registers through the MDIO 1 space as told in the datasheet. But when i try write into this memory space and read back, the data always is 0xffff.  

 

Please give us a clear picture of why and what is happening???? 

 

Regards, 

Iyan
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Altera_Forum
Honored Contributor II
258 Views

Did you set the correct PHY address first in the mdio_addr1 register? It is only if you have the correct address there that you'll get an answer from the PHY. If you don't know it's address, you can try all of them (there are only 32) and see if one of them provide you with a different answer than ffff. 

Are the MDIO lines connected from the FPGA to the PHY? Are there pull-ups?
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