Tofino 3 Details/Match-Action Table Clarification

[ThePuriProdigy]

Hi all, a common way I see pipeline architectures in devices such as the Tofino 3 switch that contain MAU units defined is each MAU has x TCAM blocks and y SRAM pages. Are the x and y amounts of TCAM/SRAM referring to the amount available solely for the key portion of a key, action, action data table? As an example, if an MAU is described as having 100 SRAM pages available and my algorithm will use 100 SRAM pages worth of keys + additional 20 pages for the action data, is that fine? Or will the action data SRAM amount also need to be factored in so that the key+action data will not exceed 100 pages total?

Also, I was wondering if there was a way to find out specific Tofino 3 specs such as the number of MAUs per pipeline and the amount of TCAM blocks/SRAM pages that they each hold?

[Mike_Intel]

Hello ThePuriProdigy,

Thank you for posting in Intel Ethernet Communities. 

For us to further check the issue, please provide the following details.

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If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.

Best regards,

Michael L.

Intel® Customer Support

[Mike_Intel]

Hello ThePuriProdigy,

I hope you're having a wonderful day. I am just sending a soft follow up on the information that we requested for us to further assist you. We will wait for your reply. 

If you have questions, please let us know. In case we do not hear from you, we will make a follow up after 3 workings days. Thank you.

Best regards,

Michael L.

Intel® Customer Support

[Mike_Intel]

Hello ThePuriProdigy,

I hope this message finds you well. I am just sending another follow up on the information that I requested. Since we have not heard back from you, I need to close this inquiry. 

If you need any additional information, please submit a new question as this thread will no longer be monitored.

Thank you and stay safe.

Best regards,

Michael L.

Intel® Customer Support