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Altera_Forum
Honored Contributor I
2,107 Views

1-wire (onewire) SOPC builder component

Hi, 

 

Project home: 

http://opencores.org/project,sockit_owm 

The source code is here: 

https://github.com/jeras/sockit_owm 

The GitHub version might be temporarily slightly ahead to the OpenCores version. 

 

RTL features: 

- small RTL, should fit into a CPLD 

- Avalon MM bus, Wishbone compatible with a simple adapter 

- timed reset, presence, write/read bit transfers 

- overdrive 

- power supply (strong pull-up) 

 

SOPC Builder integration 

 

Nios II EDS integration: 

- port of the 1-wire open domain kit version 3.10b 

- interrup driven or polling driver 

- uCOS-II support (only partialy tested) 

 

Known issues: 

- there is no automatic detection of uCOS-II so: 

-- with HAL only the polling driver works properly 

-- with uCOS-II the interrupt driven driver should be used (polling disabled) 

 

I would appreciate questions and bug reports. 

 

Note: Tar with the component was updated to Rev 5 from OpenCores.org, equivalent to hash a8dfa48 on GitHub.com 

 

Regards, 

Iztok Jeras
0 Kudos
15 Replies
Altera_Forum
Honored Contributor I
89 Views

Maxim / Dallas offers the 1-wire driver as verilog source where you only need to place an sopc builder wrapper around it to connect it to the avalon switch fabric. 

 

this driver works perfectly. 

you need to ask maxim / dallas via email to get the sources
Altera_Forum
Honored Contributor I
89 Views

I tried the Maxim VHDL code a couple years ago, and I had problems getting it to run above 50MHz on Cyclone II, but I am not sure about the details. Does this version run OK at 100MHz? 

 

Anyway, my design implements only the bit level physical layer and should therefore be much smaller. 

 

Regards, 

Iztok
Altera_Forum
Honored Contributor I
89 Views

The sources i have from Maxim / Dalles are verilog HDL sources and they run perfectly in several projects without any timing issues. I have tried them up to 96MHz but mainly at 64MHz.

Altera_Forum
Honored Contributor I
89 Views

MSchmitt, 

 

Can you post your DS1W <-> Avalon bridge code ? 

 

Thanks,
Altera_Forum
Honored Contributor I
89 Views

i can not hand out the sources i wrote as the owner is the company i work for. 

 

all you need from the maxim dallas verilog sources is the file onewiremaster.v 

 

you need some avalon interface signals like 

 

module SOPC_DS1Wire_Master (  

// Avalon Interface 

avs_DS1Wire_clk, //  

avs_DS1Wire_chipselect, //  

avs_DS1Wire_address, //  

avs_DS1Wire_read, //  

avs_DS1Wire_readdata, //  

avs_DS1Wire_write, //  

avs_DS1Wire_writedata, // 

avs_DS1Wire_byteenable, // 

avs_DS1Wire_reset, //  

avs_DS1Wire_irq, // 

avs_DS1Wire_export_DS1WireTX, // 

avs_DS1Wire_export_DS1WireRxTX // 

); 

 

and some control registers where nios sets or resets some bits and assign them to registers like 

 

// 1011  

// interrupt enable register 

// 

reg EOWL; // enable OW low interrupt 

reg EOWSH; // enable OW shorted interrupt 

reg epd; // enable presence detect interrupt 

//reg ias; // INTR active state 

reg etbe; // enable transmit buffer empty interrupt 

reg etmt; // enable transmit shift register empty int. 

reg erbf; // enable receive buffer full interrupt 

reg ersf; // enable receive shift register full int. 

////wire [ 7: 0] INTEN_REG = {EOWL, EOWSH, ersf, erbf, etmt, etbe, ias, epd}; 

//wire [ 7: 0] INTEN_REG = {EOWL, EOWSH, ersf, erbf, etmt, etbe, 1'b0 , epd}; 

 

always @ ( posedge avs_DS1Wire_clk or posedge avs_DS1Wire_reset ) // 

if ( avs_DS1Wire_reset ) // 

begin 

EOWL <= 1'b0; 

EOWSH <= 1'b0; 

ersf <= 1'b0; 

erbf <= 1'b0; 

etmt <= 1'b0; 

etbe <= 1'b0; 

// ias <= 1'b0; 

epd <= 1'b0; 

end 

else 

if ( avs_DS1Wire_chipselect && avs_DS1Wire_write && avs_DS1Wire_byteenable[0] && (avs_DS1Wire_address == 4'b1011) ) 

begin 

EOWL <= avs_DS1Wire_writedata[7]; 

EOWSH <= avs_DS1Wire_writedata[6]; 

ersf <= avs_DS1Wire_writedata[5]; 

erbf <= avs_DS1Wire_writedata[4]; 

etmt <= avs_DS1Wire_writedata[3]; 

etbe <= avs_DS1Wire_writedata[2]; 

// ias <= avs_DS1Wire_writedata[1]; 

epd <= avs_DS1Wire_writedata[0]; 

end 

 

alltogether looks pretty straight foreward what all the other files from maxim dallas did, ported to 32 bit nios world 

 

the correct tcl (part of it, company related information removed) file for the component would be 

 

# TCL File Generated by Component Editor 9.1sp1 

# Fri Mar 05 15:43:04 CET 2010 

# DO NOT MODIFY 

 

# +----------------------------------- 

# | 

# | sopc_ds1wire_master "SOPC_DS1Wire_Master" v9.1 

# | Michael Schmitt 2010.03.05.15:43:04 

# | SOPC_DS1Wire_Master 

# | 

# | ./hdl/SOPC_DS1Wire_Master.v syn 

# | ./SOPC_DS1Wire_Master.qip 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | request TCL package from ACDS 9.1 

# | 

package require -exact sopc 9.1 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | module sopc_ds1wire_master 

# | 

set_module_property DESCRIPTION SOPC_DS1Wire_Master 

set_module_property NAME sopc_ds1wire_master 

set_module_property VERSION 9.1 

set_module_property INTERNAL false 

set_module_property AUTHOR "Michael Schmitt" 

set_module_property DISPLAY_NAME SOPC_DS1Wire_Master 

set_module_property TOP_LEVEL_HDL_FILE hdl/SOPC_DS1Wire_Master.v 

set_module_property TOP_LEVEL_HDL_MODULE SOPC_DS1Wire_Master 

set_module_property INSTANTIATE_IN_SYSTEM_MODULE true 

set_module_property EDITABLE true 

set_module_property ANALYZE_HDL TRUE 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | files 

# | 

add_file hdl/SOPC_DS1Wire_Master.v SYNTHESIS 

add_file SOPC_DS1Wire_Master.qip SYNTHESIS 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | connection point DS1Wire_clock 

# | 

add_interface DS1Wire_clock clock end 

 

set_interface_property DS1Wire_clock ENABLED true 

 

add_interface_port DS1Wire_clock avs_DS1Wire_clk clk Input 1 

add_interface_port DS1Wire_clock avs_DS1Wire_reset reset Input 1 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | connection point DS1Wire_export 

# | 

add_interface DS1Wire_export conduit end 

 

set_interface_property DS1Wire_export ASSOCIATED_CLOCK DS1Wire_clock 

set_interface_property DS1Wire_export ENABLED true 

 

add_interface_port DS1Wire_export avs_DS1Wire_export_DS1WireRxTX export Bidir 1 

add_interface_port DS1Wire_export avs_DS1Wire_export_DS1WireTX export Output 1 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | connection point DS1Wire 

# | 

add_interface DS1Wire avalon end 

set_interface_property DS1Wire addressAlignment DYNAMIC 

set_interface_property DS1Wire associatedClock DS1Wire_clock 

set_interface_property DS1Wire burstOnBurstBoundariesOnly false 

set_interface_property DS1Wire explicitAddressSpan 0 

set_interface_property DS1Wire holdTime 0 

set_interface_property DS1Wire isMemoryDevice true 

set_interface_property DS1Wire isNonVolatileStorage false 

set_interface_property DS1Wire linewrapBursts false 

set_interface_property DS1Wire maximumPendingReadTransactions 0 

set_interface_property DS1Wire printableDevice false 

set_interface_property DS1Wire readLatency 0 

set_interface_property DS1Wire readWaitStates 0 

set_interface_property DS1Wire readWaitTime 0 

set_interface_property DS1Wire setupTime 0 

set_interface_property DS1Wire timingUnits Cycles 

set_interface_property DS1Wire writeWaitTime 0 

 

set_interface_property DS1Wire ASSOCIATED_CLOCK DS1Wire_clock 

set_interface_property DS1Wire ENABLED true 

 

add_interface_port DS1Wire avs_DS1Wire_chipselect chipselect Input 1 

add_interface_port DS1Wire avs_DS1Wire_address address Input 4 

add_interface_port DS1Wire avs_DS1Wire_read read Input 1 

add_interface_port DS1Wire avs_DS1Wire_write write Input 1 

add_interface_port DS1Wire avs_DS1Wire_writedata writedata Input 32 

add_interface_port DS1Wire avs_DS1Wire_byteenable byteenable Input 4 

add_interface_port DS1Wire avs_DS1Wire_readdata readdata Output 32 

# | 

# +----------------------------------- 

 

# +----------------------------------- 

# | connection point DS1Wire_irq 

# | 

add_interface DS1Wire_irq interrupt end 

set_interface_property DS1Wire_irq associatedAddressablePoint DS1Wire 

 

set_interface_property DS1Wire_irq ASSOCIATED_CLOCK DS1Wire_clock 

set_interface_property DS1Wire_irq ENABLED true 

 

add_interface_port DS1Wire_irq avs_DS1Wire_irq irq Output 1 

# | 

# +-----------------------------------
Altera_Forum
Honored Contributor I
89 Views

Hi, 

 

The onewire RTL is now tested, and I modified the Maxim 1-wire public domain kit (version 3.1) to be able to read the temperature from DS18B20. 

 

But now I have problems packaging the the modified parts of the public domain kit into a HAL (later uC-OS II). I have written the *_sw.tcl file, but SOPC Builder is reporting an error while parsing it, and Nios II EDS did not integrate the specified files into the BSP. 

 

The error is the same as mentioned here: 

http://www.alteraforum.com/forum/showthread.php?t=19616 

I am running quartus on Ubuntu Lucid, but I had the same problem on CentOS, would the WinXP version do better? 

 

Does anybody have any experience on how to fix it. 

 

I would also have some HAL driver related questions if someone is able to help: 

module_INSTANCE(name, state) usually creates a global (is it) structure with the name given to the module in SOPC Builder. But the Maxim public domain kit is not written to support multiple instances in a SoC is it ok to use a structure with a fixed name? 

 

The source code is here: 

http://github.com/jeras/fpga-hdl/tree/master/hdl/onewire/ 

 

Regards, 

Iztok Jeras
Altera_Forum
Honored Contributor I
89 Views

I found the problem, the supported hardware version in the *_sw.tcl file was wrong so the driver was not instantiated. 

 

Regards, 

Iztok
Altera_Forum
Honored Contributor I
89 Views

Hi, 

 

I updated the 1-wire master SOPC Builder component. There are now more configuration options, and dividers are computed automatically from the system clock. So integration into SOPC builder should be trivial, but there is still some coding and documenting to do regarding software. 

 

The SOPC Builder component (documentation and drivers included) is available here: 

https://github.com/jeras/sockit_owm/tree/master/sockit_owm/ 

 

A demo implementation is available here: 

https://github.com/jeras/sockit_owm/tree/master/demo/ 

 

If you are interested into this project please ask me for help. 

I am able to get the temperature from a sensor, for now I can send you a .tar of my project workplace. 

I should be able to get the software demo on github in the next month. 

 

Regards, 

Iztok Jeras
Altera_Forum
Honored Contributor I
89 Views

Hi, 

 

Has this core been used with Quartus 11.0 and Qsys? I am having some problems getting my system to work. When running Analysis and Synthesis I get the following error: 

 

Error: Sopc_system.sockit_owm_0: Component sockit_owm 1.3 not found 

 

I had no problem adding the core in Qsys. 

 

Any input would be greatly appreciated! 

 

Thank you, 

- Curtis
Altera_Forum
Honored Contributor I
89 Views

Hi Curtis, 

 

This component has not yet been tested with Qsys, also there were some bugs in the version uploaded to OpenCores, and the version provided here, the latest version is available from: 

https://github.com/jeras/sockit_owm 

if you are not used to git, this is a tar package (available by clicking the download button): 

https://github.com/jeras/sockit_owm/tarball/master 

 

I will have time this weekend to build a clean project in Qsys and test again at least the default configuration. 

 

I seems that you are the first real user or this project, so I will be happy to help with any issues. 

 

Regarding the error, I am not sure right now, what it would be, the tools search for the component in a set of directories, one of them is the project directory, so the easiest way to make the component available is to copy it to the project directory. But it might be that I did something wrong regarding my version numbers. 

 

Also I think the name of the component instance should be 'onewire' due to some stuff in the software driver. I will check this and if this is really a requirement, and add code that will generate an error it the name is wrong. 

 

If you need this quickly you could check the demo project (demo directory) for clues. 

 

Regards, 

Iztok Jeras
Altera_Forum
Honored Contributor I
89 Views

I have the latest version that you recommended. There is not a huge rush, so I will wait for you to check out your driver in Qsys. I need to use the current version of Quartus and Qsys, and I figure that getting it to work with the latest software is a good plan regardless. 

 

Again, thank you for your help. 

 

- Curtis
Altera_Forum
Honored Contributor I
89 Views

Hi Curtis, 

 

I started with a fresh project for the DE1 board and was able to build it hardware and run the software. I did not encounter the same problem you did, I copied the sockit_owm directory inside the Quartus project directory, so I do not get what the problem with your project is. 

 

There is a small issue with clock calculation. When you add the sockit_owm component the tool will complain about a divide by zero, this error will go away as soon as a clock is connected to the component, I will try to add a check so that a more descriptive error would be given. 

 

I also encountered problems with the software. The default software configuration is with interrupts enabled. But it seems interrupts only work properly if UCOS-II is used. I have yet to find a proper fix for this issue. For now set the pooling driver option in the BSP editor. 

 

Regards, 

Iztok Jeras
Altera_Forum
Honored Contributor I
89 Views

Hi Iztok, 

 

I got it to compile. It turns out that I didn't have the sockit_owm directory inside the project directory. This seems to make a difference even if the Qsys IP search path is set to the sockit_owm directory. 

 

Thank you for your help. I will proceed and let you know if I run into other problems. 

 

Best, 

 

- Curtis
Altera_Forum
Honored Contributor I
89 Views

Hi Curtis, 

 

The "Qsys IP search path" should point to the parent directory of the components. For example if you have many custom made components inside one directory, you have to add a single path. 

 

Do you plan to use UCOS-II, or simply HAL? 

 

I am looking forward to your progress. I have spent a lot of time writing and testing this code, but is is hard to find other developers willing to test it. 

 

Regards, 

Iztok Jeras
Altera_Forum
Honored Contributor I
89 Views

Hello, 

 

Ich work with an Altera de0 Board an am Maxim DS2218. I have a One-Wire-Code from Maxim. I implemented to the SOPC Builder and now I must write an Avalon MM Master. 

How can I write it? can you help me? 

 

Regards
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