17044 error while running the analysis and synthesis in the design

[SERMASWATHIKA]

Hi Team,

    i have created on qsys design which contains NIOS II processor + ddr3 + other ips+ custom logic in cyclone v gx device.

with this i tried to compile the design in quartus 22.1 tool, i am facing 17044 error.

my design top file is bdf file. i cannot modify as customer recommending that. Please guide me to resolve this.

[ShengN_Intel]

Hi,

Check this https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#msgs/msgs/escl_scl_illegal_wys_io_ibuf.htm

Thanks,

Best Regards,

Sheng

[SERMASWATHIKA]

Hi ,

  If the error is for Custom RTL , i can modify the io connection. But the error is throwing ddr3 ip library file connected in qsys. Even i tried one of the solution shared in intel forum that make qsys file as top file. And observed no error for qsys top file. But if i make bdf file as top, i am getting this error.

[ShengN_Intel]

Hi,

Because in the BDF, there're connections made to the ddr3. Probably there're inappropriate connections to the ddr3 i/o. Does the error still occur if removing connections to the ddr3 in BDF? If no, probably this is related to ddr3 connection problem, may need to open a new thread with title target ddr3 to get related expert help.

Thanks,

Sheng

[SERMASWATHIKA]

ok , maybe i will create another threat. Thanks!