ALT2GXB Help................

[Altera_Forum]

Hi, 

 I am using the ALT2GXB with the Stratix II GX ep2sgx90ff1508c3 board... I configured the GXB using the Mega core from the quartus...  When I run the GXB on the hardware the recieved data is different from the transmitted data.. Actually I gave the output of the counter(16bit counter running at 312.5MHz) as the transmitter input to the GXB.... I used the Locations as G1,G4 in the FPGA as the RXDATA & TXDATA (serial lines) connected to the HSMA TX_P3 & HSMA_RX_P3 pair....  I have attached the BDF file that I used as my design.Also the CSV file obtained while running the Signal tap II analyser....  DO i have missed anything while configuring the ALT2GXB.....  Thanks Santosh

[Altera_Forum]

--- Quote Start ---   can you please explain me how we can use these in the pcie identification.......  --- Quote End ---  PCIe device identification is identical to PCI device identification. The configuration space of the device contains device and manufacturer IDs, and contains the number of BARS, their sizes, whether they are prefetchable, etc.  These parameters are entered by the user when designing the PCIe IP core. I haven't use Altera's PCIe core (other than to test their reference designs), but I imagine there is a place in the MegaWizard to override the PCIe IDs, or at least the subvendor IDs.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---    I saw in the document Stratix II GX PCI Express Development Board that is present in the following link   www.altera.com/literature/manual/mnl-s (http://www.altera.com/literature/manual/mnl-s)2gx-pci-express-devkit.pdf  in the fpp configuration section(page 24) we have the figure 2–8. which explains the concept for the pcie configuration, in this we have to select config_mode[1:0] as "00" & dipsw+pgm[2:0] for the configuration file page select - 0,1,2.....  in the same pdf under the max ii cpld configuration controller(page 27) it was told to use the pfl mega function .....  can you please explain me how we can use these in the pcie identification.......  --- Quote End ---  These references have nothing to do with PCIe identification, they're related to configuring FPGAs. Here's a more detailed reference on that subject, perhaps it is clearer;  http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/fpga_configuration.pdf)  Cheers, Dave

[Altera_Forum]

Thank you very much Sir for your reply ..........