Hello,
I am using the ALTLVDS_RX IP Core to deserialize data from TI's ADS5263 EVM (16 bit, quad channel, 100MSps ADC). I am using a DE2-115 board (Cyclone IV E). The ADC provides a DDR bit clock (8*fs) and a frame clock (=fs). When the data is aligned, the frame should read 0xFF00. The problem I am having is that the frame does not stay aligned. In order to read valid data I have to pulse the rx_data_align signal 16 times, essentially running through all of the possible frame alignments, every time. This causes incoming samples to be missed while the frame is not aligned. Does anyone have any ideas as to why this may be?
Some more details: I currently have one data channel and the frame clock as inputs to the ALTLVDS block. I am using fs = 20MHz and 16x deserialization. I saw in the IP Core User Guide that Cyclone devices only support up to 10x deserialization, but Quartus does not complain when I enter 16 as the SERDES factor in the Megafunction Wizard.
The rx_data_align pulse is controlled by a state machine. Below are a picture of my Verilog code for the state machine, as well as what I am seeing with Signal Tap.
Any suggestions would be much appreciated.
Thanks,
Hannah
