FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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I have Altera Stratix II GX PCI-E development kit, which has four Micron MT47H32M16CC 16bit data width and one Micron MT47H32M8BP 8bit width memory chips (total 72 bits). 

This allows me to use DDR2 memory with ECC option, however I am failing to make it work. There are no examples of Nios systems for S2GX to show the full capabilities of such memory device combinations. UDP Offload example use only that 8bit memory chip. 

Problem reproducing: 

1. I add ALTMEMPHY controller for DDR2 in SOPC Builder. Refclk=100MHz, Memory clock freq=200MHz. 

2. Since the tool has some presets, I select Micron MT47H32M16C-3 x4 + MT47H32M8BP-3 x1 preset. 

3. Under Controller Settings tab I enable error detection and correction logic and also enable error auto correction. 


The pin locations are taken from an example of high speed pci-e to ddr2 example project. Too bad it doesn't use Nios II. 


The whole system is clocked from memory_sysclk (which is 200MHz as I mentioned before). The system runs from on-chip memory (.bss/.heap/etc, size of the memory: 131072 bytes) and I am trying to check the memory using memory test example provided by software build tools in Eclipse. The cpu starts, memory check program also starts, but when I enter start address and end address, it shows that the memory check has started and hangs up (even if I check e.g. 0x10000000 to 0x10000001). 


Schematics shows address pins connected up to A15 (A13,A14,A15 are marked as RFU) plus BA2 is also connected to the FPGA, but marked as RFU too. SOPC generates address output A[0:12] and bank access BA[0:1]. Why those pins are connected if the pins on DDR2 chip are not used afaik? 


Maybe someone use such 72bit ECC configuration? Are there any examples of such system setup?
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